HYMD512G726A4-M Datasheet, PDF (11/17 Pages) Hynix Semiconductor – Registered DDR SDRAM DIMM

HYMD512G726A(L)4-M/K/H/L
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
- continued -
Parameter
-M(DDR2662-2-2) -K(DDR266A)
Symbol
Min Max Min Max
Input Hold Time (slow slew rate)
tIH
1.0
-
1.0
-
Input Pulse Width
tIPW
2.2
-
2.2
-
Write DQS High Level Width
tDQSH 0.35
-
0.35
-
Write DQS Low Level Width
tDQSL 0.35
-
0.35
-
Clock to First Rising edge of
DQS-In
tDQSS 0.75 1.28 0.75 1.25
Data-In Setup Time to DQS-In
(DQ & DM)
tDS
0.5
-
0.5
-
Data-in Hold Time to DQS-In (DQ
& DM)
tDH
0.5
-
0.5
-
DQ & DM Input Pulse Width
tDIPW 1.75
-
1.75
-
Read DQS Preamble Time
tRPRE 0.9
1.1
0.9
1.1
Read DQS Postamble Time
tRPST 0.4
0.6
0.4
0.6
Write DQS Preamble Setup Time tWPRES 0
-
0
-
Write DQS Preamble Hold Time tWPREH 0.25
-
0.25
-
Write DQS Postamble Time
tWPST 0.4
0.6
0.4
0.6
Mode Register Set Delay
tMRD
2
-
2
-
Exit Self Refresh to Any Execute
Command
tXSC
200
-
200
-
Average Periodic Refresh Interval tREFI
-
7.8
-
7.8
-H(DDR266B)
Min Max
1.0
-
2.2
-
0.35
-
0.35
-
0.75 1.25
0.5
-
0.5
-
1.75
-
0.9
1.1
0.4
0.6
0
-
0.25
-
0.4
0.6
2
-
200
-
-
7.8
-L(DDR200)
Min Max
1.1
-
2.5
-
0.35
-
0.35
-
Unit Note
ns
2,4,5,
6
ns 6
CK
CK
0.75 1.25 CK
0.6
-
ns
6,7,
11~13
0.6
-
ns
6,7,
11~13
2
-
ns
0.9
1.1 CK
0.4
0.6 CK
0
-
CK
0.25
-
CK
0.4
0.6 CK
2
-
CK
200
-
CK 8
-
7.8 us
Note :
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation
7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
Rev. 0.2 / Feb. 2004
11