H5TQ1G63DFR Datasheet, PDF (109/172 Pages) Hynix Semiconductor – 1Gb DDR3 SDRAM

ODT pin
0
1
Table 23. Termination Truth Table
DRAM Termination State
OFF
On, (OFF, if disabled by MR1 {A9, A6, A2} and MR2 {A10, A9} in general)
3.2 Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down
definition, these modes are:
• Any bank active with CKE high
• Refresh with CKE high
• Idle mode with CKE high
• Active power down mode (regardless of MR0 bit A12)
• Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12.
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be dis-
abled by continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2}
to {0,0,0} via a mode register set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising
clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT
latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL -2.
3.2.1 ODT Latency and Posted ODT
In Synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also
applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by
the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2;
ODTLoff = CWL + AL - 2. For details, refer to ODT Timing Parameters listed in Table 52 on page 150 and
Table 53 on page 159.
3.2.2 Timing Parameters
In synchronous ODT mode, the following timing parameters apply (see also Figure 76):
ODTLon, ODTLoff, t_AON,min,max, t_AOF,min,max.
Minimum RTT turn-on time (t_AONmin) is the point in time when the device leaves high impedance and ODT
resistance begins to turn on. Maximum RTT turn on time (t_AONmax) is the point in time when the ODT
resistance is fully on. Both are measured from ODTLon.
Minimum RTT turn-off time (t_AOFmin) is the point in time when the device starts to turn off the ODT resistance.
Maximum RTT turn off time (t_AOFmax) is the point in time when the on-die termination has reached high
impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the
SDRAM with ODT high, then ODT must remain high until ODTH4 (BL = 4) or ODTH8 (BL = 8) after the Write
command (see Figure 77). ODTH4 and ODTH8 are measured from ODT registered high to ODT registered
low or from the registration of a Write command until ODT is registered low.
Rev. 1.1 /Jan. 2011
109