GMS97C2051 Datasheet, PDF (10/39 Pages) Hynix Semiconductor – 8-Bit CMOS Microcontorller

GMS97C2051/L2051
8-Bit CMOS Microcontroller
Idle Mode
In idle mode, the CPU puts itself to sleep while all the
on-chip peripherals remain active. The mode is in-
voked by software. The content of the on-chip RAM
and all the special functions registers remain unchanged
during this mode. The idle mode can be terminated by
any enabled interrupt or by a hardware reset. P1.0 and
P1.1 should be set to ‘0’ if no external pullups are used,
or set to ‘1’ if external pullups are used.
It should be noted that when idle is terminated by a
hardware reset, the device normally resumes program
execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in
this event, but access to the port pins is not inhibited.
To eliminate the possibility of an unexpected write to a
port pin when Idle is terminated by reset, the instruc-
tion following one that invokes Idle should not be one
that writes to a port pin or to external memory.
Power Down Mode
GMS97C2051/L2051 have two power saving modes,
Idle and Power Down. The bits PD and IDLE of the
register PCON select the Power Down mode and the
Idle mode, respectively. If 1s are written to PD and
IDLE at the same time, PD takes precedence. Table 9
gives a general overview of the Power saving modes. In
the Power Down mode of operation, V_CC can be re-
duced to minimize power consumption. It must be
ensured, however, that Vcc is not reduced before the
Power Down mode is invoked, and that Vcc is restored
to its normal operating level, before the Power Down
mode is terminated. The reset signal that terminates
the Power down mode also restarts the oscillator. The
reset should not be activated before Vcc is restored to
its normal operating level and must be held active long
enough to allow the oscillator to restart and stabilize.
( similar to power-on reset ).
Table 9. Power Saving Modes Overview
Mode
Idle mode
Ex. instruction to enter
ORL PCON, #01H
To terminate
Enabled interrupt,
Hardware Reset
Power-down Mode ORL PCON, #02H Hardware Reset
Remarks
- CPU is gated off
- CPU status registers maintain their data.
- Peripherals are active
- Oscillator stops
- Contents of on-chip RAM and SFRs are
maintained
- Reset redefines all the SFRs but does not
change the on-chip RAM
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