HY57V121620 Datasheet, PDF (1/12 Pages) Hynix Semiconductor – 4 Banks x 8M x 16Bit Synchronous DRAM

HY57V121620(L)T
4 Banks x 8M x 16Bit Synchronous DRAM
DESCRIPTION
The HY57V121620 is a 512-Mbit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large mem-
ory density and high bandwidth. HY57V121620 is organized as 4banks of 8,388,608x16.
HY57V121620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage
levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply
• Auto refresh and self refresh
• All device pins are compatible with LVTTL interface
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin • Programmable Burst Length and Burst Type
pitch
- 1, 2, 4, 8 or Full page for Sequential Burst
• All inputs and outputs referenced to positive edge of sys-
tem clock
- 1, 2, 4 or 8 for Interleave Burst
• Data mask function by UDQM, LDQM
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY57V121620T-6
HY57V121620T-K
HY57V121620T-H
HY57V121620T-8
HY57V121620T-P
HY57V121620T-S
HY57V121620LT-6
HY57V121620LT-K
HY57V121620LT-H
HY57V121620LT-8
HY57V121620LT-P
HY57V121620LT-S
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Power
Normal
Low power
Organization
4Banks x 8Mbits x16
Interface
Package
LVTTL
400mil 54pin TSOP II
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev.0.3/Dec. 01
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