HDMP-0440 Datasheet, PDF (6/10 Pages) Agilent(Hewlett-Packard) – Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops

AC Electrical Specifications
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V.
Symbol
Parameter
TLOOP_LAT
Total Loop Latency from FM_NODE[0] to TO_NODE[0]
TCELL_LAT
Per Cell Latency from FM_NODE[4] to TO_NODE[0]
tr,LVTTLin
Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V
tf,LVTTLin
Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V
tr,LVTTLout
Output TTL Rise Time, 0.8 V to 2.0 V, 10 pF Load
tf,LVTTLout
Output TLL Fall Time, 2.0 V to 0.8 V, 10 pF Load
trs,HS_OUT
HS_OUT Single-Ended Rise Time, 20% to 80%
tfs,HS_OUT
HS_OUT Single-Ended Fall Time, 20% to 80%
trd,HS_OUT
HS_OUT Differential Rise Time, 20% to 80%
tfd,HS_OUT
HS_OUT Differential Fall Time, 20% to 80%
VIP,HS_IN
HS_IN Required Pk-Pk Differential Input Voltage
VOP,HS_OUT HS_OUT Pk-Pk Differential Output Voltage (Z0 = 75 Ω, Figure 6)
Units Min.
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
mV
200
mV
1100
Typ. Max.
2.0
0.8
2.0
2.0
1.7 3.3
1.7 2.4
200 30
200 300
200 300
200 30
1200 2000
1400 2000
Guaranteed Operating Rates
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V.
FC Serial Clock Rate (MBd)
Min.
Max.
GE Serial Clock Rate (MBd)
Min.
Max.
1,040
1,080
1,240
1,260
Figue 4. Eye diagram of TO_NODE[1]± high speed differential output (50 Ω termination).
Note: Measurement taken with a 2⁷-1 PRBS input to FM_NODE[1]±.
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