HCTL-2000 Datasheet, PDF (5/18 Pages) Agilent(Hewlett-Packard) – Quadrature Decoder/Counter Interface ICs

Switching Characteristics
Table 5. Switching Characteristics Min/Max specifications at V_DD = 5.0 ± 5%, T_A = -40 to + 85°C.
Symbol Description
Min. Max. Units
1 t_CLK Clock period
2 t_CHH Pulse width, clock high
3 t_CD[1] Delay time, rising edge of clock to valid, updated count
information on D0-7
70
ns
28
ns
65
ns
4 t_ODE Delay time, OE fall to valid data
5 t_ODZ Delay time, OE rise to Hi-Z state on D0-7
6 t_SDV Delay time, SEL valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
65
ns
40
ns
65
ns
7 t_CLH Pulse width, clock low
28
ns
8 t_SS[2] Setup time, SEL before clock fall
20
ns
9 t_OS[2] Setup time, OE before clock fall
20
ns
10 t_SH[2] Hold time, SEL after clock fall
0
ns
11 t_OH[2] Hold time, OE after clock fall
0
ns
12 t_RST Pulse width, RST low
28
ns
13 t_DCD Hold time, last position count stable on D0-7 after clock rise 10
ns
14 t_DSD Hold time, last data byte stable after next SEL state change
5
ns
15 t_DOD Hold time, data byte stable after OE rise
5
ns
16 t_UDD Delay time, U/D valid after clock rise
45
ns
17 t_CHD Delay time, CNT_DCDR or CNT_CAS high after clock rise
45
ns
18 t_CLD Delay time, CNT_DCDR or CNT_CAS low after clock fall
45
ns
19 t_UDH Hold time, U/D stable after clock rise
10
ns
20 t_UDCS Setup time, U/D valid before CNT_DCDR or CNT_CAS rise
t_CLK-45
ns
21 t_UDCH Hold time, U/D stable after CNT_DCDR or CNT_CAS rise
t_CLK-45
ns
Notes:
1. t_CD specification and waveform assume latch not inhibited.
2. t_SS, t_OS, t_SH, t_OH only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup
and hold times do not need to be observed.
Figure 3. Tri-State Output Timing.
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