RGR2622 Datasheet, PDF (2/6 Pages) Agilent(Hewlett-Packard) – Fiber Optic “Light to Logic” Receiver with Clock Recovery

Connection Diagram
Top View
FIBER PIGTAIL
GND
1
GND
2
GND
3
CLOCK
4
CLOCK
5
GND
6
DATA
7
GND
8
DATA
9
PD BIAS
10
20
NC
19
NC
18
NC
17
NC
16
GND
15
GND
14
ALARM
13
GND
12
ALARM
11
+5 V
Pin Descriptions
Pins 1, 2, 3, 6, 8, 13, 15, 16,
GND:
These pins should be connected
to the circuit ground.
Pins 4, 5, CLOCK, CLOCK:
These pins provide
complementary PECL CLOCK
and CLOCK outputs.
Pins 7, 9, DATA, DATA:
These pins provide complemen-
tary PECL DATA and DATA
outputs.
The RGR2622 DATA output is
noninverting, an optical pulse
causes the DATA output to go to
the PECL logic high state (+4 V
nominal).
Pin 10, PD Bias:
This pin must be connected to
any voltage from 0 V (GND) to
–5 V. This provides the photo-
diode bias. The current drawn is
directly proportional to the
average received photocurrent.
I = Responsivity x Mean Power.
The Responsivity will be between
0.8 A/W and 1.0 A/W.
Pin 11, +5 V:
This pin should be connected to
+5 V supply. The network shown
below should be placed as close
as possible to pin 11.
Pins 12, 14, ALARM, ALARM:
These pins provide complemen-
tary ALARM and ALARM outputs.
This is the low light alarm.
ALARM goes to a logic low
(CMOS compatible) state when
the optical power drops below
the threshold level (insufficient
optical power).
The optical power must increase
to a higher level than the level
where the alarm went low before
ALARM will return to a logic
high. This difference is the alarm
hysteresis.
Pins 17, 18, 19, 20 NC:
These pins are not connected.
PIN 11
10 µF
1 µH
100 nF
+5 V
100 nF
407