HPFC-5000 Datasheet, PDF (2/2 Pages) Agilent(Hewlett-Packard) – Fibre Channel Interface Controller

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Features (continued)
• Automatic ACK frame genera-
tion and processing
• On-chip support of FCP for
SCSI Initiators and Targets
• Supports up to 16,384 concur-
rent SCSI I/O transactions
• Compliant with Internet MIB-
II network management
• Direct interface to industry
standard 10 and 20-bit Giga-
bit Link Modules (GLM)
• Hardware assists for TCP/
UDP/IP networking
• Parity protection on internal
data path
• Eight internal DMA channels
• Full duplex internal architec-
ture that allows TACHYON to
process inbound and outbound
data simultaneously
BACKPLANE
TACHYON
BACKPLANE
INTERFACE
TAD [31:0]
PARITY
AVCS_L
TYPE [2:0]
READY_L
PREFETCH_L
RETRY_L
ERROR_L
INT_L
RESET_L
TBR_L [1:0]
TBG_L
SCLK
GIGABIT
LINK MODULE
INTERFACE
PAR_ID [1:0]
RX [19:0]
RBC
COM_DET
L_UNUSE
LCKREF_L
EWRAP
FAULT
TX [19:0]
Specifications
System Clock Frequency:
24-40 MHz backplane
operation
Operating Temperature:
0-50°C @ 0 m/s airflow,
0-70°C @ 1.5 m/s airflow
Testability:
Full internal scan path. IEEE
Standard 1149.1 Boundary
Scan
Packaging:
208-pin metal quad flat pack
Standards:
Intended to be compliant with
ANSI standards and FCSI/
FCA profile definitions
SCAN TEST
INTERFACE
TDI
TDO
TCK
TRST
TMS
TBC
TXCLK_SEL
LP2
Figure 3. TACHYON Pin-out Block Diagram
GIGABIT
LINK
MODULE
RX
TX
CLOCK
GENERATOR
RC
BACKPLANE
INTERFACE
CHIP
TACHYON
GIGABIT
LINK
MODULE
CLK
Figure 2. System Adapter Card Block Diagram
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Data Subject to Change
Copyright © 1996 Hewlett-Packard Co.
Printed in U.S.A. 5965-1215E (7/96)