GM5621 Datasheet, PDF (8/19 Pages) STMicroelectronics – Dual input LCD controller for entry level applications

HMC5843
Voltage Regulator
This ASIC has an internal voltage regulator which, depending on the application needs, may be used instead of supplying
voltage to pin DVDD. If DVDD pin is used, the internal voltage regulator is not engaged. When both supplies are used,
DVDD is typically high before AVDD, but no latch-up conditions will exist if DVDD is brought high after AVDD.
Power on Reset
Power on reset (POR) circuit shall return the device to the power-on default state. All registers shall be returned to their
default values. Circuitry shall return to it default state, such as, but not limited to: MUX channel, ADC state machine, and
bias current.
I²C Interface
Control of this device is carried out via the I²C bus. This device will be connected to this bus as a slave device under the
control of a master device, such as the processor.
This device shall be compliant with I²C-Bus Specification, document number: 9398 393 40011. As an I²C compatible
device, this device has a 7-bit serial address and supports I²C protocols. This device shall support standard and fast
modes, 100kHz and 400kHz respectively, but cannot support the high speed mode (Hs). External pull-up resistors are
required to support these standard and fast speed modes. Depending on the application, the internal pull-ups may be
used to support slower data speeds than specified by I²C standards. This device does not contain 50nsec spike
suppression as required by fast mode operation in the I²C-Bus Specification, “Table 4 Characteristics of the SDA and
SCL I/O stages for F/S-mode I²C-bus devices”.
Activities required by the master (register read and write) have priority over internal activities, such as the measurement.
The purpose of this priority is to not keep the master waiting and the I²C bus engaged for longer than necessary.
I²C Pull-up Resistors
Pull-up resistors are placed on the two I²C bus lines. Typically these resistors are off-chip, but, to conserve board space
in specific low clock speed applications, they are internal to this device.
Internal Clock
The device has an internal clock for internal digital logic functions and timing management.
H-Bridge for Set/Reset Strap Drive
The ASIC contains large switching FETs capable of delivering a large but brief pulse to the Set / Reset strap of the
sensor. This strap is largely a resistive load.
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