HX6408 Datasheet, PDF (1/11 Pages) Honeywell Solid State Electronics Center – 512k x 8 STATIC RAM

HX6408
Advanced Information
HX6408
512k x 8 STATIC RAM
The 512K x 8 Radiation Hardened Static RAM is a high
performance 524,288 word x 8-bit static random access
memory with optional industry-standard functionality. It is
fabricated with Honeywell’s radiation hardened Silicon On
Insulator (SOI) technology, and is designed for use in low
voltage systems operating in radiation environments. The
RAM operates over the full military temperature range and
requires only a single 3.3 V ± 0.3V power supply. Power
consumption is typically <30 mW @ 1MHz in write mode,
<14 mW @ 1MHz in read mode, and is less than 5 mW
when in standby mode.
The RICMOS™ V low power process is a SOI CMOS
technology with an 80 Å gate oxide and a minimum
drawn feature size of 0.35 µm. Additional features
include tungsten via and contact plugs, Honeywell’s
proprietary SHARP planarization process and a lightly
doped drain (LDD) structure for improved short
channel reliability. A seven transistor (7T) memory cell
is used for superior single event upset hardening,
while three layer metal power busing and the low
collection volume SOI substrate provide improved
dose rate hardening.
Honeywell’s enhanced RICMOS™(Radiation Insensitive
CMOS) SOI V technology is radiation hardened through the
use of advanced and proprietary design, layout and process
hardening techniques.
FEATURES
ƒ Fabricated with RICMOS™ V
ƒ No Latchup
ƒ Single Power Supply,
Silicon On Insulator (SOI)
3.3 V ± 0.3 V
ƒ
ƒ
ƒ
0.35 mm Process (Leff = 0.28 µm)
Total Dose ≥ 3x10⁵ and 1X10⁶ rad(SiO₂)
Neutron ≥1x10¹⁴ cm^-2
ƒ
ƒ
Read/Write Cycle Times
≤20 ns, (3.3 V), -55 to 125°C
Typical Operating Power (3.3 V)
<14 mW @ 1MHz Read
ƒ
ƒ
Operating Range is
-55°C to +125°C
36-Lead Flat Pack Package
ƒ Dynamic and Static Transient Upset
≥1x10¹⁰ rad(Si)/s (3.3 V)
<30 mW @ 1MHz Write
<5 mW Standby mode
ƒ Optional Low Power Sleep
Mode
ƒ Dose Rate Survivability ≥1x10¹² rad(Si)/s ^{ƒ Asynchronous Operation}
ƒ Soft Error Rate
≤1x10^-10 Upsets/bit-day (3.3 V)
ƒ CMOS Compatible I/O
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