HI-3717 Datasheet, PDF (7/23 Pages) Holt Integrated Circuits – Single-Rail ARINC 717 Protocol IC with SPI Interface

HI-3717
REGISTER DESCRIPTIONS (cont.)
CONTROL REGISTER 1: CTRL1
Read: SPI Op-code 0xE2
Write: SPI Op-code 0x62
XX
76
MSB
XX
54
SRSTSFTSYNNOCSYT^NECST
3210
LSB
Bit Name R/W Default Description
7-4
-
R/W 0 Not Used, Always reads a “0”
3 SRST R/W 0 Software Reset - Setting this bit to “1” empties all the FIFO’s, clears the Sync detection logic and
sets the analog line drivers to Hi-Z state. All other register bits remain unchanged.
2 SFTSYNC R/W 0 Software Synchronization - Setting the bit to “1” will result in the INSYNC output pin going high
when the third of three consecutively occurring sync marks is detected.
1 NOSYNC R/W 0 No Synchronization - Setting this bit to “1” will result in all data captured being loaded into the
receive FIFO. WARNING: In this mode there is no way the HI-3717 can determine frame or sub-
frame boundaries. This sync mode overrides all the other sync modes when set to “1”.
0 TEST R/W 0 Test Mode - A “1” in this bit position will disable the line receiver and both line drivers and the digital
transmitted data will be looped back to the HBP or BPRZ data sampler selected by RXSEL .
TABLE 4.
RECEIVE FIFO STATUS REGISTER: RXFSTAT
Read: SPI Op-code 0xE6
Write: Read Only
INSYNS^CYNCS^1YNCR^{0FFULRLFHARLFFEMRPFTOYV}T^FEST
XXXX XXXX
76543210
MSB
LSB
Bit Name R/W Default Description
7 INSYNC R
0 Receive channel sync indicator. The bit is set to”1” when synchronization is achieved on the
receive channel.
Normal synchronization occurs when four consecutive valid sync marks (Octal 1107, 2670, 5107
and 6670 respectively) are received exactly 1 second apart. The bit is set when the next valid and
properly spaced subframe sync mark (Octal 1107) is detected.
Software Synchronization (CTRL1<2> = “1”) occurs when two consecutively valid sync marks are
received exactly 1 second apart and in the proper order but the first sync mark does not have to be
Octal 1107. The bit is set when the next valid and properly spaced subframe sync mark is detected.
The bit remains set until synchronization is lost at which time the device automatically attempts to
re-synchronize. No data is passed to the receive FIFO until Synchronization is re-established.
Existing data in the FIFO remains intact and can be read at any time.
6-5 SYNC0:1 R
0 The two bits are a realtime indicators of when each of the four ARINC 717 subframe sync marks are
received. They are updated when the sync mark is detected and passed to the Receive FIFO. The
two bits are only valid when INSYNC is “1”
00 Subframe SYNC1 mark received (Octal 1107)
01 Subframe SYNC2 mark received (Octal 2670)
10 Subframe SYNC3 mark received (Octal 5107)
11 Subframe SYNC4 mark received (Octal 6670)
4 RFFULL R
0 Bit is set when the Receive FIFO contains 32 words.
3 RFHALF R
0 Bit is set when the Receive FIFO contains exactly 16 words.
2 RFEMPTY R
1 Bit is set when the Receive FIFO is empty. It is reset to”0” when the first valid word is passed to the
Receive FIFO.
1 RFOVF R
0 FIFO Overflow bit and ROVF pin are set to “1” when devices attempts to load a valid word to a full
Receive FIFO. The Receive FIFO will ignore additional words if it is full.
0
-
R
0 Not used, Always reads “0”
TABLE 5.
HOLT INTEGRATED CIRCUITS
7