AN-550 Datasheet, PDF (4/11 Pages) Holt Integrated Circuits – This application note provides recommendations

AN-550
Shading
Represents
Internal Ground
Plane Layer
22uF 5V
SMD Tantalum
Capacitor
Two 100nF
SMD 0805
Chip Caps
HI-6110PQ
52-PQFP
GND Pin
MAGNIFIED
DETAIL
Via to
VCC Plane
PM-DB2745S
Isolation
Transformer
Transformer-Coupled Bus A
BUS A
BUS A
BUS B
BUS B
Two 55 Ohm
SMD 2512 Resistors for
Direct-Coupled Bus B
Via to
GND Plane
Example Circuit Board Layout for HI-6110
Explanatory Notes:
1. Component sizes are approximately to scale. Compromises were necessary in trying to portray a multilayer
design in a single graphic. The layout assumes conventional 4-layer construction with internal Ground and Power
planes and external signal routing layers on top and bottom. The black trace segment should be routed on the
bottom of the board.
2. The layout shows Bus A configured as transformer-coupled and Bus B configured as direct coupled (having 55
Ohm isolation resistors). A conventional layout would probably not use mixed coupling modes. Notice that the HI-
6110 uses the same 2.50:1 transformer turns ratio for both coupling methods.
3. Bus connectors and pictured circuitry are placed close to board edge to minimize crosstalk.
4. No Ground plane or Power plane is poured under the transformer or analog bus signals to minimize shunt
capacitance which affects terminal input impedance at high frequency. The light grey area represents the region
where Ground and Power planes are present.
5. Circuit board “vias” make connections between layers.
6. All three surface mount capacitors have vias connecting both ends to their respective Ground and VCC planes.
Where space permits, 2 doubled-up vias on power and ground terminals (and high current signal conductors)
provide a current path with lower inductance than a single via.
7. Ideally, the 22uF bulk storage capacitor would be placed on the bottom, located closer to the two 100nF
capacitors with (+) side connected to the VDD-Power vias for both 100nF capacitors.
Figure 3. EXAMPLE CIRCUIT BOARD LAYOUT FOR PROTOCOL DEVICE
HOLT INTEGRATED CIRCUITS
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