HI-6135 Datasheet, PDF (39/172 Pages) Holt Integrated Circuits – 40 MHz SPI Host Interface

HI-6135
9.12. Memory Address Pointer Registers
The Serial Peripheral Interface (SPI) uses predefined 8-bit instruction op codes to perform a variety of predetermined
actions. Some op codes must be followed by two or more operand bytes, while other SPI codes perform their desired
action without additional operands. Examples of self-contained SPI op codes include the “Fast access” op codes used
for reading or writing registers at the low end of the address space.
“Fast access” op codes used for direct addressing contain embedded register addresses, but only work over a limited
address range.
• SPI reads to register addresses 0 through 0x000F (decimal 15) use an 8-bit op code of the form
0x00 + (Reg_Addr << 2) where Reg_Addr = 0 to 0xF before left-shifting two bits.
• SPI writes to register addresses 0 through 0x003F (decimal 63) use an 8-bit op code of the form
0x80 + Reg_Addr where Reg_Addr equals 0 to 0x3F.
The two “fast access” op codes use a dedicated memory address pointer to perform their duties without affecting
values contained in other Memory Address Pointer registers. The “fast access” Memory Address Pointer cannot be
read by the host, but is written each time a “fast access” op code is processed.
The HI-6135 uses a Memory Address Pointer for SPI reads to register addresses over 0x000F, or for SPI writes
to register addresses over 0x003F. For most SPI read and write operations, the starting memory address for the
requested operation is written to the Memory Address Pointer (or MAP) before the op code (using the MAP) is invoked.
In the case of a multiword data transfer involving a range of sequential addresses, the memory address pointer is
initialized with the starting (lowest) address. After the SPI transfers data from the first address, the memory address
pointer automatically increments to the next address. When read access occurs, the device prefetches the data stored
at the next address to support the fastest possible data rates. As long as the chip select stays low (asserted) and the
SPI master continues to provide serial clocks, data read/write transfers for sequential addresses continue until the chip
select is negated. Please refer to section “Host Serial Peripheral Interface (SPI)” on page 128, describing SPI host
access and the SPI op codes used for data transfer.
For flexibility in configuring the device, four independent Memory Address Pointers are available. These can be
assigned in any manner that supports application requirements. For example:
• Consider using a dedicated Memory Address Pointer for interrupt service routines. Many SPI operations are
multiword transfers that utilize the Memory Address Pointer auto-increment feature. If interrupts are enabled
during multiword transfers, a dedicated Memory Address Pointer for the interrupt service routine avoids corruption
of the MAP used by the interrupted routine.
Residing in the lower register address space, the four Memory Address Pointers can be read or written with a single
8-bit “fast access” op code (plus the desired 16-bit data value, when writing).
Just one of the four MAP registers is enabled at any time. Each of the four Memory Address Pointers has a dedicated
8-bit “MAP Select” op code that enables it by writing the “Master Configuration Register 1 (0x0000)”. Or the host can di-
rectly write the MAPSEL (Memory Address Pointer select) bits 11-10 in the “Master Configuration Register 1 (0x0000)”
to enable the desired MAP register. Full descriptions of SPI data transfer methods are provided later in this document.
The four memory address pointer registers are:
MAP1 Memory Address Pointer Register
MAP2 Memory Address Pointer Register
MAP3 Memory Address Pointer Register
MAP4 Memory Address Pointer Register
0x000B
0x000C
0x000D
0x000E
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