HI-8582_13 Datasheet, PDF (3/16 Pages) Holt Integrated Circuits – ARINC 429 System on a Chip

HI-8582, HI-8583
FUNCTIONAL DESCRIPTION
CONTROL WORD REGISTER
The HI-8582/HI-8583 contain a 16-bit control register which is
used to configure the device. The control register bits CR0 - CR15
are loaded from BD00 - BD15 when CWSTR is pulsed low. The
control register contents are output on the databus when SEL = 1
and RSR is pulsed low. Each bit of the control register has the
following function:
STATUS REGISTER
The HI-8582/HI-8583 contain a 9-bit status register which can be
interrogated to determine the status of the ARINC receivers, data
FIFOs and transmitter. The contents of the status register are
output on BD00 - BD08 when the RSR pin is taken low and
SEL = 0. Unused bits are output as Zeros. The following table
defines the status register bits.
CR
Bit ^FUNCTION
CR0
Receiver 1
Data clock
Select
CR1 Label Memory
Read / Write
CR2
CR3
CR4
CR5
Enable Label
Recognition
(Receiver 1)
Enable Label
Recognition
(Receiver 2)
Enable
32nd bit
as parity
Self Test
CR6
Receiver 1
decoder
CR7
-
CR8
-
CR9
Receiver 2
Decoder
CR10
-
CR11
-
CR12
CR13
CR14
CR15
Invert
Transmitter
parity
Transmitter
data clock
select
Receiver 2
data clock
select
Data
format
STATE
DESCRIPTION
0
Data rate = CLK/10
1
Data rate = CLK/80
0
Normal operation
1
Load 16 labels using PL1 / PL2
Read 16 labels using EN1 / EN2
0
Disable label recognition
1
Enable label recognition
0
Disable Label Recognition
1
Enable Label recognition
0
Transmitter 32nd bit is data
1
Transmitter 32nd bit is parity
0
The transmitter’s digital
outputs are internally connected
to the receiver logic inputs
1
Normal operation
0
Receiver 1 decoder disabled
1
ARINC bits 9 and 10 must match
CR7 and CR8
-
If receiver 1 decoder is enabled,
the ARINC bit 9 must match this bit
-
If receiver 1 decoder is enabled,
the ARINC bit 10 must match this bit
0
Receiver 2 decoder disabled
1
ARINC bits 9 and 10 must match
CR10 and CR11
-
If receiver 2 decoder is enabled,
the ARINC bit 9 must match this bit
-
If receiver 2 decoder is enabled,
the ARINC bit 10 must match this bit
0
Transmitter 32nd bit is Odd parity
1
Transmitter 32nd bit is Even parity
0
Data rate=CLK/10, O/P slope=1.5us
1
Data rate=CLK/80, O/P slope=10us
0
Data rate=CLK/10
1
Data rate=CLK/80
0
Scramble ARINC data
1
Unscramble ARINC data
SR
Bit ^{FUNCTION STATE}
DESCRIPTION
SR0 Data ready
(Receiver 1)
0
Receiver 1 FIFO empty
1
Receiver 1 FIFO contains valid data
Resets to zero when all data has
been read. D/R1 pin is the inverse of
this bit
SR1 FIFO half full
(Receiver 1)
0
Receiver 1 FIFO holds less than 16
words
1
Receiver 1 FIFO holds at least 16
words. HF1 pin is the inverse of
this bit.
SR2
FIFO full
(Receiver 1)
0
Receiver 1 FIFO not full
1
Receiver 1 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF1 pin is
the inverse of this bit
SR3 Data ready
(Receiver 2)
0
Receiver 2 FIFO empty
1
Receiver 2 FIFO contains valid data
Resets to zero when all data has
been read. D/R2 pin is the inverse of
this bit
SR4 FIFO half full
(Receiver 2)
0
Receiver 2 FIFO holds less than 16
words
1
Receiver 2 FIFO holds at least 16
words. HF2 pin is the inverse of
this bit.
SR5
FIFO full
(Receiver 2)
0
Receiver 2 FIFO not full
1
Receiver 2 FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period. FF2 pin is
the inverse of this bit
SR6 Transmitter FIFO
0
empty
1
Transmitter FIFO not empty
Transmitter FIFO empty.
SR7 Transmitter FIFO
0
full
1
Transmitter FIFO not full
Transmitter FIFO full. FFT pin is the
inverse of this bit.
SR8 Transmitter FIFO
0
half full
Transmitter FIFO contains less than
16 words
1
Transmitter FIFO contains at least
16 words.HFT pin is the
inverse of this bit.
HOLT INTEGRATED CIRCUITS
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