HI-3210_13 Datasheet, PDF (29/43 Pages) Holt Integrated Circuits – ARINC 429 DATA MANAGEMENT ENGINE

HI-3210
PENDING INTERRUPT REGISTER
(Address 0x800A)
COPYA^{EURTROCEHRKRERRARMFFALIAL GATXRDY}
XX
76543210
MSB
LSB
The MINT will be asserted when any of the bits in this register are set.
Bit Name
7 COPYERR
6 AUTOERR
5 CHKERR
4 RAMFAIL
3 FLAG
2 ATXRDY
1-
0-
R/W Default Description
R
0 EE copy error. RAM - EEPROM mismatch
R
0 Auto-inititailization RAM read error
R
0 Auto-initialization checksum fail
R
0 Power-On Reset RAM Integrity Check fail
R
0 Logical OR of ARINC 429 Receive FIFO FLAG signals
R
0 ARINC 429 Host TX ready. Used with Host SPI op-code 100101TT (see Table 1). Interrupt
when any of the four ARINC 429 transmitters are ready for the next 32-bit word from the host
R
0 Not Used
R
0 Not Used
PENDING INTERRUPT ENABLE REGISTER
(Address 0x8034)
COPYA^{EURTROCEHRKRERRARMFFALIAL GAIETXRDYIE}
XX
76543210
MSB
LSB
Bit Name
7 COPYERR
6 AUTOERR
5 CHKERR
4 RAMFAIL
3 FLAGIE
2 ATXRDYIE
1-
0-
R/W Default Description
R
1 COPYERR is not maskable
R
1 AUTOERR is not maskable
R
1 CHKERR is not maskable
R
1 RAMFAIL is not maskable
R/W 0 MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register FLAG bit is set
R/W 0 MINT pin is asserted if this bit is a “1” and the Pending Interrupt Register ATXRDY bit is set
R/W 0 Not Used
R/W 0 Not Used
HOLT INTEGRATED CIRCUITS
29