HI-6130 Datasheet, PDF (120/290 Pages) Holt Integrated Circuits – 3.3V BC / MT / RT Multi-Terminal Device

HI-6130, HI-6131
Bit No. Mnemonic
12 EO
R/W Reset Function
Error Occurred Flag.
This bit indicates a message error was encountered. This bit is set when
one or more of the following conditions are true (logical-OR):
R/W 0
• an unfinished message is superseded by another valid command
• Bit 10 Illegal Gap Error is set
• Bit 9 Response Timeout is set
• Bit 5 Length (Word Count) Error is set
• Bit 4 Sync Type Error is set
• Bit 3 Invalid Word Error is set
• Bit 2 RT-RT Gap / Sync / Address Error is set
• Bit 1 RT-RT Command Word 2 Error is set (except as noted)
• Bit 0 Command Word Content Error is set (except as noted)
11 RR
10 IGE
9
TM
Three exceptions where register bit 0 or 1 is set without affecting bit 12
state:
Bit 1 RT-RT Command Word 2 Errors that do not assert bit 12
• RT-RT Transmit Command Word 2 subaddress field equals 00000
or 11111 (mode code command indicated)
• RT-RT Transmit Command Word 2 has the same RT Address as
Receive Command Word 1
Bit 0 Command Word Content Error that does not assert bit 12
• Undefined receive mode code 0~15 decimal.
RT-to-RT Transfer
R/W 0 _{When logic 1, bit 11 indicates an RT-to-RT message, beginning with two}
contiguous Command Words.
Illegal Gap Error
R/W 0 ^{When logic 1, bit 10 indicates an illegal gap occurred on the bus, other}
than Response Timeout. The IRIG-106 Standard refers to this bit as
Format Error, having the same definition.
Response Timeout.
When logic 1, bit 9 indicates a response timeout occurred. This bit is
set if an RT Status Word associated with this message failed to arrive
R/W
0
within the response time interval specified by bits 15-14 in the MT
Configuration Register 0x0029.
For IRIG-106 compatibility, bits 15-14 in register 0x0029 should be
initialized to 00, corresponding to a 14µs response time, as defined by
MIL-STD-1553B (12µs bus dead time).
HOLT INTEGRATED CIRCUITS
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