HI-8483 Datasheet, PDF (1/11 Pages) Holt Integrated Circuits – ARINC 429 Dual Line Receiver

February 2012
HI-8483
ARINC 429
Dual Line Receiver
GENERAL DESCRIPTION
The HI-8483 bus interface unit is a dual differential line re-
ceiver in accordance with the requirements of the ARINC
429 bus specification. The device translates incoming
ARINC 429 signals to normal CMOS/TTL levels on each
of its two independent receive channels. The HI-8483 is
a functional alternative to the Fairchild/Raytheon
RM3283 and DEI3283.
Two TTL compatible self-test inputs for testing the ARINC
channels are available. They can be used to override the
ARINC input data and set the channel outputs to a known
state. The self-test mode checks the entire circuit includ-
ing the analog line receivers and digital logic.
All the ARINC inputs have built-in hysteresis to reject
noise that may be present on the ARINC bus. Additional
input noise filtering can also be accomplished with exter-
nal capacitors.
The HI-8483 is available in a variety of ceramic & plastic
packages including Small Outline (SOIC), DIP &
Leadless Chip Carrier (LCC).
FEATURES
• ^{Replacement for RM3283 and DEI3283}
• ^{Converts ARINC 429 levels to digital data}
• ^{Input hysteresis for superior noise rejection}
• ^{TTL and CMOS outputs and test inputs}
• ^{Military screening available}
• ^{20-Pin SOIC, DIP &}
LCC packages are available
PIN CONFIGURATIONS (Top Views)
-VS - 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+VL - 9
N/C - 10
HI-8483PSI
HI-8483PST
HI-8483PSM
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +VS
20 - Pin Plastic Small Outline package (SOIC)
(See ordering information for additional pin configurations)
-V_S - 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+V_L - 9
N/C - 10
HI-8483CRI
HI-8483CRT
HI-8483CRM
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +V_S
20 - Pin Ceramic Dual In Line package (CERDIP)
(See ordering information for additional pin configurations)
ARINC INPUTS
V (A) - V (B)
Null
Zero
One
Don't Care
Don't Care
Don't Care
TRUTH TABLE
TEST INPUTS
TEST A TEST B
0
0
0
0
0
0
0
1
1
0
1
1
OUTPUTS
OUT A OUT B
0
0
0
1
1
0
0
1
1
0
0
0
(DS8483 Rev. A)
HOLT INTEGRATED CIRCUITS
www.holtic.com
02/12