HI-6120PQI Datasheet, PDF (1/116 Pages) Holt Integrated Circuits – MIL-STD-1553 Remote Terminal ICs

November 2009
HI-6120 Parallel Bus Interface and
HI-6121 Serial Peripheral Interface (SPI)
MIL-STD-1553 Remote Terminal ICs
GENERAL DESCRIPTION
The HI-6120 and HI-6121 provide a complete, integrated,
3.3V MIL-STD-1553 Remote Terminal in a monolithic
silicon gate CMOS device. Two host interface options are
offered: The HI-6120 uses a 16-bit parallel host bus
interface for access to registers and RAM and is offered in
a 100-pin plastic quad flat pack (PQFP). The HI-6121 has a
4-wire SPI (Serial Peripheral Interface) host connection
and comes in a reduced pin count 52-pin PQFP or 64-pin
QFN. Both devices handle all aspects of the MIL-STD-
1553 protocol, including message encoding, decoding,
error detection, illegal command detection and data
buffering. Host data management is simplified by storing
message information and data within the on-chip 32K x 16
static RAM.
A descriptor table in shared RAM provides fully
programmable memory management. Multiple descriptor
tables can be implemented for fast context switching.
Transmit and receive commands can use any of four
different data buffer modes: indexed (single) buffering,
ping-pong (double) buffering or two circular buffer
schemes. Transmit and receive commands for each
subaddress may use different buffer modes. Mode code
commands employ a simple scheme for storing mode data
and message information with programmable interrupts.
The device provides internal illegalization capability,
allowing any subset of subaddress, command T/R bit,
broadcast vs non-broadcast and word count (or mode
code) to be illegalized, resulting in a total of 4,096 possible
combinations. The illegalization table resides in internal
RAM. The RT can also operate without illegal command
detection, providing “in form” responses to all valid
commands. Broadcast command recognition is optional.
REMOTE TERMINAL FEATURES
· Fully integrated 3.3V Remote Terminal meets all
requirements for MIL-STD-1553B Notice 2
· Four data buffer methods for subaddress transmit and
receive commands: indexed (single) buffering, ping-
pong (double) buffering and two circular buffer modes
· Independently selectable data buffer modes for
transmit and receive commands on each subaddress
· Simplified mode code command handling
· Integral 16-bit Time-Tag counter has programmable
options for clock, interrupts and auto-synchronization
· Message information and time-tag words are stored
with message data words for all transacted messages
· In compliance with MIL-STD-1553B Notice 2, received
data from broadcast messages may be optionally
separated from non-broadcast received data
· Optional interrupt log buffer stores the most recent 16
interrupts to minimize host service duties
· Optional illegal command detection uses internal table
· Optional automatic self-initialization at reset
· +/- 8kV ESD Protection (HBM, all pins)
· MIL-STD-1760 compliant
PIN CONFIGURATION (Top View)
HI-6121 in 52-PQFP Package
The HI-6120 and HI-6121 provide programmable
interrupts for automatic message handling, message
status and general status. A host interrupt history log
maintains information about the last 16 interrupts.
The HI-6120 and HI-6121 can be configured for automatic
self-initialization. A dedicated SPI port reads data from
external serial EEPROM memory to fully configure the
descriptor table, illegalization table and host interrupts.
COMP - 1
CE - 2
MODE - 3
SI - 4
SCK - 5
SO - 6
MCLK - 7
RTA0 - 8
RTA1 - 9
RTA2 - 10
MR - 11
RTA3 - 12
RTA4 - 13
Internal dual-redundant transceivers provide direct
connection to bus isolation transformers. The device is
offered with industrial temperature range. Extended
temperature range is also offered, with optional burn-in. A
“RoHS compliant” lead-free option is offered.
HI-6120 Rev New
HOLT INTEGRATED CIRCUITS
www.holtic.com
HI-6121PQx
39 - TEST
38 - LOCK
37 - MTSTOFF
36 - BUSA
35 - VCCP
34 - BUSA
33 - BUSB
32 - VCCP
31 - BUSB
30 - TEST0
29 - TEST1
28 - TEST2
27 - TEST3
11/09