HI-6110_10 Datasheet, PDF (1/38 Pages) Holt Integrated Circuits – MIL-STD-1553 / MIL-STD-1760 MIL-STD-1553 / MIL-STD-1760

May 2010
HI-6110
MIL-STD-1553 / MIL-STD-1760
BC / RT / MT Message Processor
GENERAL DESCRIPTION
The HI-6110 is a CMOS integrated circuit implementing the
MIL-STD-1553 (1553) data communications protocol
between a host processor and a dual redundant 1553 data
bus. The single chip architecture has a digital section
containing all necessary logic and memory to process and
store the command and data words for one complete 1553
message. The analog section includes dual transceivers
coupled to the 1553 buses through external current mode
transformers. The device is available in an industry standard
64-pin 9 mm square QFN package, making it the smallest
dual redundant 1553 interface product on the market.
The HI-6110 may be configured as a Bus Controller (BC), a
Remote Terminal (RT), a Monitor Terminal (MT), or a Monitor
Terminal with assigned RT address. 16-bit registers store
incoming and outgoing Command, Status and Data words.
Using two 32-word data FIFOs, the HI-6110 can store the
maximum number of 1553 words occurring in any message.
For messages with transmitted data words, data may be
written in advance or on-the-fly. Received data can be
retrieved on-the-fly or all at once after the Valid Message flag
is asserted.
BC message sequences are initiated by a rising edge on the
BCSTART input, or a 0 to 1 transition at the BCSTART bit in
the Control Register. All RT command responses are
automatically initiated after a valid Command Word is
received.
A single encoder services both buses, each of which have a
dedicated analog transformer driver. Each driver dissipates
less than 200 mW of on-chip power at 100% duty cycle.
Each bus receiver has a dedicated Manchester decoder. In
BC mode, a RCV signal indicates when valid 1553 words are
received. In RT/MT modes, RCV indicates a valid command
received, while the 1553 command decoder updates a
Message register so the external controller can identify
command type and respond appropriately. Guaranteed by
design, the HI-6110 cannot generate messages exceeding
660uS, the duration of a Command or Status Word plus 32
contiguous data words.
The external host controller reads and writes a simplified
register structure in the HI-6110 over a 16-bit parallel bus.
The system designer has flexibility over many aspects of
configuration. Control and status monitoring can be done in
hardware (by reading/writing control pins) or in software (by
reading/writing register bits).
FEATURES
• Monolithic CMOS Technology
• 3.3V operation
• Exceptionally low power
• On-chip message buffering
• Selectable master clock frequency
• Dual differential 1553 bus transceivers
• Bus Controller / Remote Terminal /
Monitor Terminal operating modes
• Compliant to MIL-STD-1553B Notice 2
and MIL-STD-1760 Stores Management
APPLICATIONS
• MIL-STD-1553 Terminals
• Flight Control and Monitoring
• ECCM Interfaces
• Stores Management
• Test Equipment
• Sensor Interfaces
• Instrumentation
PIN CONFIGURATION (Top View)
R/W - 1
CS - 2
D0 - 3
D1 - 4
D2 - 5
D3 - 6
D4 - 7
D5 - 8
D6 - 9
D7 - 10
D8 - 11
D9 - 12
D10 - 13
HI-6110PQI
&
HI-6110PQT
39 - VDDA
38 - BUSA
37 - BUSB
36 - VDDB
35 - BUSB
34 - TXINHB
33 - RCVB
32 - FFEMPTY
31 - RF0 / RCMDA
30 - RF1 / RCMDB
29 - RFLAG
28 - VALMESS
27 - ERROR
52 Pin Plastic Quad Flat Pack (PQFP)
See page 35 for 64-Pin QFN Pin Configuration
(DS6110 Rev. R)
HOLT INTEGRATED CIRCUITS
www.holtic.com
05/10