BS84B08A-3 Datasheet, PDF (98/123 Pages) Holtek Semiconductor Inc – A/D Type Touch Key MCU

BS84B08A-3/BS84C12A-3
A/D Type Touch Key MCU
TBC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TB1
TB0
—
—
—
—
R/W
—
—
R/W
R/W
—
—
—
—
POR
—
—
0
0
—
—
—
—
Bit 7~6
Bit 5~4
Bit 3~ 0
Unimplemented, read as “0”
TB1 ~ TB0: Select Time Base Time-out Period
00: 1024/fTP
01: 2048/fTP
10: 4096/fTP
11: 8192/fTP
Unimplemented, read as “0”
fS Y S
fS U B
0M
U
fT P
1X
TB 1~TB 0
¸ 2 ^{1 0}~ 2 ^{1 3}
T im e B a s e
T S B it
Time Base Structure
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timer interrupt enable bit, TE, must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag, TF, is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack
is not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer
interrupt vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TF,
will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
EEPROM Interrupt
An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set,
which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit,
DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write
cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the
EEPROM Interrupt is serviced, the DEF flag will be automatically cleared and the EMI bit will be
automatically cleared to disable other interrupts.
Rev. 1.00
98
May 02, 2013