BS86B12A-3 Datasheet, PDF (93/195 Pages) Holtek Semiconductor Inc – Touch A/D Flash MCU with LED/LCD Driver

BS86B12A-3/BS86C16A-3/BS86D20A-3
Touch A/D Flash MCU with LED/LCD Driver
PTMnRPH Register
Bit
7
6
5
4
3
Name
—
—
—
—
—
R/W
—
—
—
—
—
POR
—
—
—
—
—
Bit 7 ~ 2
Bit 1 ~ 0
Unimplemented, read as “0”
PTMn CCRP High Byte Register Bit 1 ~ Bit 0
PTMn 10-Bit CCRP Bit 9 ~ Bit 8
2
1
0
—
D9
D8
—
R/W
R/W
—
0
0
Periodic Type TM Operating Modes
The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the PTnM1 and PTnM0 Bits in the PTMnC1 register.
Compare Match Output Mode
To select this mode, Bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00
respectively. In this mode once the counter is enabled and running it can be cleared by three
methods. These are a counter overflow, a compare match from Comparator A and a compare match
from Comparator P. When the PTnCCLR Bit is low, there are two ways in which the counter can be
cleared. One is when a compare match from Comparator P, the other is when the CCRP Bits are all
zero which allows the counter to overflow. Here both PTMAnF and PTMPnF interrupt request flags
for Comparator A and Comparator P respectively, will both be generated.
If the PTnCCLR Bit in the PTMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the PTMAnF interrupt request flag will be
generated even if the value of the CCRP Bits is less than that of the CCRA registers. Therefore
when PTnCCLR is high no PTMPnF interrupt request flag will be generated. In the Compare Match
Output Mode, the CCRA can not be cleared to zero.
If the CCRA Bits are all zero, the counter will overflow when its reaches its maximum 10-Bit, 3FF
Hex, value, however here the PTMAnF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the PTM output pin, will change
state. The PTM output pin condition however only changes state when a PTMAnF interrupt request
flag is generated after a compare match occurs from Comparator A. The PTMPnF interrupt request
flag, generated from a compare match occurs from Comparator P, will have no effect on the PTM
output pin. The way in which the PTM output pin changes state are determined by the condition of
the PTnIO1 and PTnIO0 Bits in the PTMnC1 register. The PTM output pin can be selected using
the PTnIO1 and PTnIO0 Bits to go high, to go low or to toggle from its present condition when a
compare match occurs from Comparator A. The initial condition of the PTM output pin, which is
setup after the PTnON Bit changes from low to high, is setup using the PTnOC Bit. Note that if the
PTnIO1 and PTnIO0 Bits are zero then no pin change will take place.
Rev. 1.40
93
December 05, 2016