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HT9B95 Datasheet, PDF (9/32 Pages) Holtek Semiconductor Inc – RAM Mapping 39×8 / 43×4 LCD Driver
HT9B95A/B/G
Symbol
fLCD1
fLCD2
VPOR
RRVDD
tPOR
Parameter
LCD Frame Frequency
LCD Frame Frequency
VDD Start Voltage to
ensure Poewr-on Reset
VDD Rise Rate to ensure
Power-on Reset
Minimum Time for VDD to
remain at VPOR to ensure
Power-on Reset
VDD
3.3V
2.4~
5.5V
—
—
—
Test condition
condition
Ta=25°C, internal oscillator is used,
LCD frame frequency = 80 Hz
Ta=25°C, internal oscillator is used,
LCD frame frequency = 71 Hz
Ta=25°C, internal oscillator is used,
LCD frame frequency = 64 Hz
Ta=25°C, internal oscillator is used,
LCD frame frequency = 50Hz
Ta=-40 to 85°C, internal oscillator is used,
LCD frame frequency = 80 Hz
Ta=-40 to 85°C, internal oscillator is used,
LCD frame frequency = 71 Hz
Ta=-40 to 85°C, internal oscillator is used,
LCD frame frequency = 64 Hz
Ta=-40 to 85°C, internal oscillator is used,
LCD frame frequency = 50Hz
—
—
—
Min.
72
63.9
57.6
45
56
49.7
44.8
35.2
—
0.05
10
Typ.
80
71
64
50
80
71
64
50
—
—
—
Max. Unit
88
78.1
Hz
70.4
55
104
92.3
Hz
83.2
65
100 mV
— V/ms
— ms
I2C Interface Characteristics
Unless otherwise specified, VSS = 0 V; VDD = 2.4V to 5.5V; Ta=-40 to +85°C
Symbol
Parameter
Condition
Min. Max. Unit
fSCL
tBUF
tHD: STA
tLOW
tHIGH
Clock frequency
bus free time
Start condition hold time
SCL Low time
SCL High time
—
—
Time in which the bus must be free before a
new transmission can start
1.3
After this period, the first clock pulse is
generated.
0.6
—
1.3
—
0.6
400 kHZ
— μs
— μs
— μs
— μs
tSU: STA
Start condition setup time
Only relevant for repeated START condition. 0.6 — μs
tHD: DAT
Data hold time
—
tSU: DAT
Data setup time
—
tR
SDA and SCL rise time
Note
tF
SDA and SCL fall time
Note
0
— ns
100 — ns
— 0.3 μs
— 0.3 μs
tSU: STO
Stop condition set-up time
—
0.6 — μs
tAA
Output Valid from Clock
—
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
Note: These parameters are periodically sampled but not 100% tested.
— 0.9 μs
— 50 ns
Rev. 1.10
9
November 25, 2015