BS82B12A-3 Datasheet, PDF (83/170 Pages) Holtek Semiconductor Inc – Touch Flash MCU with LED/LCD Driver

BS82B12A-3/BS82C16A-3/BS82D20A-3
Touch Flash MCU with LED/LCD Driver
Timer/Counter Mode
To select this mode, bits CT0M1 and CT0M0 in the CTM0C1 register should be set to 11
respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output
Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the
CTM0 output pin is not used. Therefore the above description and Timing Diagrams for the
Compare Match Output Mode can be used to understand its function. As the CTM0 output pin is not
used in this mode, the pin can be used as a normal I/O pin or other pin-shared function.
PWM Output Mode
To select this mode, bits CT0M1 and CT0M0 in the CTM0C1 register should be set to 10
respectively. The PWM function within the CTM0 is useful for applications which require functions
such as motor control, heating control, illumination control etc. By providing a signal of fixed
frequency but of varying duty cycle on the CTM0 output pin, a square wave AC waveform can be
generated with varying equivalent DC RMS values.
As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated
waveform is extremely flexible. In the PWM mode, the CT0CCLR bit has no effect on the PWM
operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one
register is used to clear the internal counter and thus control the PWM waveform frequency, while
the other one is used to control the duty cycle. Which register is used to control either frequency
or duty cycle is determined using the CT0DPX bit in the CTM0C1 register. The PWM waveform
frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers.
An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match
occurs from either Comparator A or Comparator P. The CT0OC bit In the CTM0C1 register is used
to select the required polarity of the PWM waveform while the two CT0IO1 and CT0IO0 bits are
used to enable the PWM output or to force the CTM0 output pin to a fixed high or low level. The
CT0POL bit is used to reverse the polarity of the PWM output waveform.
CTM, PWM Mode, Edge-aligned Mode, CT0DPX=0
CCRP
Period
Duty
001b
128
010b
256
011b
384
100b
101b
512
640
CCRA
110b
768
111b
896
000b
1024
If fSYS = 16MHz, CTM0 clock source is fSYS/4, CCRP = 100b, CCRA =128,
The CTM0 PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%.
If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the
PWM output duty is 100%.
CTM, PWM Mode, Edge-aligned Mode, CT0DPX=1
CCRP
Period
Duty
001b
128
010b
256
011b
384
100b
101b
CCRA
512
640
110b
768
111b
896
000b
1024
The PWM output period is determined by the CCRA register value together with the CTM0 clock
while the PWM duty cycle is defined by the CCRP register value.
Rev. 1.60
83
December 15, 2016