HT83XXX Datasheet, PDF (8/21 Pages) Holtek Semiconductor Inc – Q-Voice

Preliminary
HT83XXX
Functional Description
Execution Flow
The system clock for the HT83XXX series is derived
from RC oscillator. It is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
Program Counter - PC
The 11-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2
S y s te m C lo c k
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt or return from subroutine, the PC
manipulates the program transfer by loading the ad-
dress corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle takes its place while the correct instruction is ob-
tained.
The lower byte of the program counter (PCL) is a
read/write register (06H). Moving data into the PCL per-
forms a short jump. The destination must be within 256
locations.
When a control transfer takes place, an additional
dummy cycle is required.
T3 T4 T1 T2 T3 T4
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
Execution Flow
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Mode
Initial Reset
Time Base Overflow
Timer Counter 0 Overflow
Timer Counter 1 Overflow
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
*10 *9
0
0
0
0
0
0
0
0
*10 *9
#10 #9
S10 S9
Program Counter
*8 *7 *6 *5 *4 *3 *2 *1 *0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
PC+2
*8 @7 @6 @5 @4 @3 @2 @1 @0
#8 #7 #6 #5 #4 #3 #2 #1 #0
S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
Program Counter
S10~S0: Stack register bits
@7~@0: PCL bits
Rev. 0.10
8
August 25, 2003