HT1622 Datasheet, PDF (8/17 Pages) Holtek Semiconductor Inc – RAM Mapping 32x8 LCD Controller for I/O xC

W R ,R D 90%
C lo c k
50%
10%
t_f
t_r
t_{C LK}
t_{C LK}
Figure 1
CS
W R ,R D
C lo c k
50%
t_su1
t_{C S}
t_h1
50%
F IR S T
C lo c k
LA S T
C lo c k
Figure 3
V _DD
DB
GND
W R ,R D
C lo c k
V _DD
GND
V _DD
GND
V A L ID D A T A
50%
t_su
t_h
50%
Figure 2
HT1622
V _DD
GND
V _DD
GND
Functional Description
Display memory - RAM structure
The static display RAM is organized into 64´4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be ac-
cessed by the READ, WRITE and
READ-MODIFY-WRITE commands. The fol-
lowing is a mapping from the RAM to the LCD
patterns.
Time base and Watchdog Timer (WDT)
The time base generator and WDT share the
same divided (/256) counter. TIMER
DIS/EN/CLR, WDT DIS/EN/CLR and IRQ
EN/DIS are independent from each other. Once
the WDT time-out occurs, the IRQ pin will re-
main at logic low level until the CLR WDT or
the IRQ DIS command is issued.
COM 7 COM 6 COM 5 COM 4
COM 3 COM 2 COM 1 COM 0
SEG 0
1
0
SEG 1
3
2
SEG 2
5
SEG 3
7
4
6
A d d r e s s 6 B its
(A 5 , A 4 , ...., A 0 )
S E G 31
63
62
A ddr
A ddr
D3
D2
D1
D0
D a ta
D3
D2
D1
D0
D a ta
D a ta 4 B its
(D 3 , D 2 , D 1 , D 0 )
RAM mapping
8
April 21, 2000