HT66F0172 Datasheet, PDF (78/115 Pages) Holtek Semiconductor Inc – Enhanced A/D Flash 8-Bit MCU

HT66F0172/HT66F0174
Enhanced A/D Flash 8-Bit MCU
fSYS
1MHz
2MHz
4MHz
8MHz
12MHz
period, tADCK, is from 0.5μs to 10μs, care must be taken for selected system clock frequencies.
For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should
not be set to 000B or 110B. Doing so will give A/D clock periods that are less than the minimum A/
D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D
conversion values.
Refer to the following table for examples, where values marked with an asterisk * show where,
depending upon the device, special care must be taken, as the values may be less than the specified
minimum A/D Clock Period.
ADCK2,
ADCK1,
ADCK0
=000
(fSYS)
1μs
500ns
250ns*
125ns*
83ns*
ADCK2,
ADCK1,
ADCK0
=001
(fSYS/2)
2μs
1μs
500ns
250ns*
167ns*
ADCK2,
ADCK1,
ADCK0
=010
(fSYS/4)
4μs
2μs
1μs
500ns
333ns*
A/D clock Period (tADCK)
ADCK2,
ADCK1,
ADCK0
=011
(fSYS/8)
ADCK2,
ADCK1,
ADCK0
=100
(fSYS/16)
8μs
16μs*
4μs
8μs
2μs
4μs
1μs
2μs
667ns*
1.33μs
ADCK2,
ADCK1,
ADCK0
=101
(fSYS/32)
32μs*
16μs*
8μs
4μs
2.67μs
ADCK2,
ADCK1,
ADCK0
=110
(fSYS/64)
64μs*
32μs*
16μs*
8μs
5.33μs
ADCK2,
ADCK1,
ADCK0
=111
Undefined
Undefined
Undefined
Undefined
Undefined
A/D Clock Period Examples
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the
ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no
pins are selected for use as A/D inputs by clearing the ACE7~ACE0 bits in the ACERL registers, if
the ADOFF bit is zero then some power will still be consumed. In power conscious applications it
is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D
converter function is not being used.
The reference voltage supply to the A/D Converter can be supplied from either the positive power
supply pin, AVDD, or from an external reference sources supplied on pin VREF. The desired
selection is made using the VREFS bit. As the VREF pin is pin-shared with other functions, when
the VREFS bit is set high, the VREF pin function will be selected and the other pin functions will be
disabled automatically.
A/D Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port A as well as other
functions. The ACE7~ ACE0 bits in the ACERL registers, determine whether the input pins are setup
as A/D converter analog inputs or whether they have other functions. If the ACE7~ ACE0 bits for its
corresponding pin is set high then the pin will be setup to be an A/D converter input and the original
pin functions disabled. In this way, pins can be changed under program control to change their
function between A/D inputs and other functions. All pull-high resistors, which are setup through
register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note
that it is not necessary to first setup the A/D pin as an input in the PAC or PBC port control registers
to enable the A/D input as when the ACE7~ ACE0 bits enable an A/D input, the status of the port
control register will be overridden.
The A/D converter has its own reference voltage pin, VREF, however the reference voltage can
also be supplied from the power supply pin, a choice which is made through the VREFS bit in the
ADCR1 register. The analog input values must not be allowed to exceed the value of VREF.
Rev. 1.00
78
July 11, 2013