HT69F240 Datasheet, PDF (72/172 Pages) Holtek Semiconductor Inc – I/O 8-Bit Flash MCU with LED/LCD Driver

HT69F240
I/O 8-Bit Flash MCU with LED/LCD Driver
Compact Type TM Operating Modes
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and CTM0
bits in the CTMC1 register.
Compare Match Output Mode
To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to 00 respectively.
In this mode once the counter is enabled and running it can be cleared by three methods. These are
a counter overflow, a compare match from Comparator A and a compare match from Comparator
P. When the CTCCLR bit is low, there are two ways in which the counter can be cleared. One is
when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero
which allows the counter to overflow. Here both CTMAF and CTMPF interrupt request flags for the
Comparator A and Comparator P respectively, will both be generated.
If the CTCCLR bit in the CTMC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the CTMAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
CTCCLR is high no CTMPF interrupt request flag will be generated. If the CCRA bits are all zero,
the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the
CTMAF interrupt request flag will not be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin will change state.
The TM output pin condition however only changes state when a CTMAF interrupt request flag is
generated after a compare match occurs from Comparator A. The CTMPF interrupt request flag,
generated from a compare match occurs from Comparator P, will have no effect on the TM output
pin. The way in which the TM output pin changes state are determined by the condition of the
CTIO1 and CTIO0 bits in the CTMC1 register. The TM output pin can be selected using the CTIO1
and CTIO0 bits to go high, to go low or to toggle from its present condition when a compare match
occurs from Comparator A. The initial condition of the TM output pin, which is setup after the
TnON bit changes from low to high, is setup using the CTOC bit. Note that if the CTIO1 and CTIO0
bits are zero then no pin change will take place.
Rev. 1.20
72
March 25, 2015