HTG2150_02 Datasheet, PDF (7/38 Pages) Holtek Semiconductor Inc – 8-Bit 320 Pixel Dot Matrix LCD MCU Series

HTG2150
Functional Description
Execution flow
The system clock for the HTG2150 is derived from an
RC oscillator. The system clock is internally divided into
four non-overlapping clocks. One instruction cycle con-
sists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program counter - PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 8192
addresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m
C lo c k
PC
PC
PC +1
PC +2
. e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
. e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
. e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
1 3 b its
P ro g ra m
C o u n te r
S ta c k
B ank0
B ank1
0000H
1...H
8 1 9 2 ´1 6
B its
2000H
3...H
B a n k P o in te r
R e g is te r B it5
R O M A d d re s s
A 1 3 b it L a tc h
L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n
1 6 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e
Mode
Initial reset
External interrupt
Timer counter 0 overflow
Timer 2 overflow
Timer 3 overflow
D/A buffer empty interrupt
Skip
Loading PCL
Jump, call branch
Return from subroutine
Program Rom Address
*13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
0 0 0 000 0 0 0 0 0 0 0 0
0 0 0 000 0 0 0 0 0 1 0 0
0 0 0 000 0 0 0 0 1 0 0 0
0 0 0 000 0 0 0 1 0 0 0 0
0 0 0 000 0 0 0 1 0 1 0 0
0 0 0 000 0 0 0 1 1 0 0 0
PC+2
*13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
BP.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Note: *13~*0: Program ROM address
@7~@0: PCL bits
#12~#0: Instruction code bits
Program rom address
S13~S0: Stack register bits
BP.5: Bit 5 of bank pointer (04H)
Rev. 1.30
7
May 21, 2002