HT46R016 Datasheet, PDF (68/91 Pages) Holtek Semiconductor Inc – Enhanced A/D Type 8-Bit OTP MCU

HT46R016/HT46R017
Enhanced A/D Type 8-Bit OTP MCU
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked
by resetting the EMI bit.
HT46R016
Interrupt Source
External interrupt
Timer/Event Counter 0 overflow
A/D Conversion Complete
Time Base Overflow
Priority
1
2
3
4
Vector
04H
08H
0CH
10H
HT46R017
Interrupt Source
External interrupt
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
A/D Conversion Complete
Time Base Overflow
Priority
1
2
3
4
5
Vector
04H
08H
0CH
10H
14H
In cases where both external and internal interrupts are enabled and where an external and internal
interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be
serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent
simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable
bit, INTE, must first be set. An actual external interrupt will take place when the external interrupt
request flag, INTF, is set, a situation that will occur when an edge transition appears on the external
INT line. The type of transition that will trigger an external interrupt, whether high to low, low to
high or both is determined by the INTEG0 and INTEG1 bits, which are bits 6 and 7 respectively, in
the CTRL0 control register. These two bits can also disable the external interrupt function.
INTEG1
0
0
1
1
INTEG0
0
1
0
1
Edge Trigger Type
External interrupt disable
Rising edge Trigger
Falling edge Trigger
Both edge Trigger
The external interrupt pin is pin-shared with the I/O pin PA3 and can only be configured as an
external interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has
been set and the edge trigger type has been selected using the CTRL0 register. The pin must also
be setup as an input by setting the corresponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and a transition appears on the external interrupt pin, a
subroutine call to the external interrupt vector at location 04H, will take place. When the interrupt is
serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will
be automatically cleared to disable other interrupts. Note that any pull-high resistor connections on
this pin will remain valid even if the pin is used as an external interrupt input.
Rev. 1.00
68
July 16, 2012