HT66F24D_13 Datasheet, PDF (55/175 Pages) Holtek Semiconductor Inc – A/D Flash Type 8-bit MCU with EEPROM

A/D Flash Type 8-bit MCU with EEPROM
HT66F24D/HT66F25D
Watchdog Time-out Reset during SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds
of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack
Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for
tSST details.
W D T T im e - o u t
tS S T
In te rn a l R e s e t
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC.
The SST is 128 clock cycles for HXT. The SST is 1~2 clock cycles for LIRC.
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. These flags, known
as PDF and TO are located in the status register and are controlled by various microcontroller
operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are
shown in the table:
TO PDF
RESET Conditions
0
0 Power-on Reset
u
u
LVR reset during NORMAL or SLOW Mode
operation
1
u
WDT time-out reset during NORMAL or
SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP
Mode operation

Note: “u” stands for unchanged.
The following table indicates the way in which the various components of the microcontroller are
affected after a power-on reset occurs.
Item
Condition After Power-on Reset
Program Counter
Reset to zero
Interrupts
All interrupt will be disabled
WDT, Time Base
Clear after reset, WDT begins counting
Timer Modules
Timer Counter will be turned off
Input/Output Ports
I/O ports will be setup as inputs and AN0~AN7 as
A/D input pins
Stack Pointer
Stack Pointer will point to the top of the stack
Rev. 1.10
55
March 25, 2013