L6713A Datasheet, PDF (53/64 Pages) Holtek Semiconductor Inc – 2/3 Phase controller with embedded drivers for Intel VR10, VR11 and AMD 6 bit CPUs

L6713A
System control loop compensation
Removing the dependence from the Error Amplifier gain, so assuming this gain high
enough, and with further simplifications, the control loop gain results:
GLOOP(s) = –⁴⁵-- ⋅
------^V----^I---^N--------
∆VOSC
⋅
-^Z---^F-----⁽--^s----⁾
RFB
⋅
R_{-----O------+-----}R_{-----D----R-----O-----O------P--}
RO
+
R_-----L--
N
⋅
----------------------------¹-----+-----^s----^â‹------^C----^O-------^â‹-----⁽---^R----^D-----^R-----^O-----^O-----^P-----^/-^/---^R----^O------+-----^E-----^S----^R-----⁾----------------------------
s2 ⋅
CO ⋅
--^L--
N
+
s
⋅
----------^L-----------
N ⋅ RO
+
CO
⋅
ESR + CO ⋅
R_-----L--
N
+1
The system Control Loop gain (See Figure 26) is designed in order to obtain a high DC gain
to minimize static error and to cross the 0dB axes with a constant -20dB/dec slope with the
desired crossover frequency ω_T. Neglecting the effect of Z_F(s), the transfer function has one
zero and two poles; both the poles are fixed once the output filter is designed (LC filter
resonance ω_LC) and the zero (ω_ESR) is fixed by ESR and the Droop resistance.
Figure 26. Equivalent Control Loop Block Diagram (left) and Bode Diagram (right).
VREF
PWM
d V_OUT L / N
V_OUT
ESR
C_O
R_O
dB
G_LOOP(s)
DROOP FB
COMP VSEN
Z_F(s)
R_F
C_F
C_P
FBG
K
R_F[dB]
Z_FB(s)
R_FB
ω_LC = ω_F
ω_ESR
Z_F(s)
ω
ω_T
To obtain the desired shape an R_F-C_F series network is considered for the Z_F(s)
implementation. A zero at ω_F=1/R_FC_F is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero ω_F in correspondence with the L-
C resonance assures a simple -20dB/dec shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results to be at
frequency lower than the above reported zero.
Compensation network can be simply designed placing ω_F = ω_LC and imposing the cross-
over frequency ω_T as desired obtaining (always considering that ω_T might be not higher than
1/10th of the switching frequency F_SW):
R_F
=
R_{-----F---B-----}⋅_------∆_----V_{----O----S---C--}
V_IN
⋅
5_--
4
⋅
ω_T ⋅
----------------------------^L------------------------------
N ⋅ (R_DROOP + ESR)
C_F
=
-----^C----^O-----^â‹------^N--L----
R_F
Moreover, it is suggested to filter the high frequency ripple on the COMP pin adding also a
capacitor between COMP pin and FB pin (it does not change the system bandwidth:
C_P
=
----------------------------¹------------------------------
2 ⋅ π ⋅ R_F ⋅ N ⋅ F_SW
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