HT82A623R Datasheet, PDF (50/98 Pages) Holtek Semiconductor Inc – A/D Type Full Speed USB 8-Bit MCU with SPI

HT82A623R/HT82A6208/HT82A6216
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
USB Interrupt
1
0004H
External Interrupt
2
0008H
Timer/Event Counter 0 Overflow
Interrupt
3
000CH
SPI_A Interrupt
4
0010H
SPI_B Interrupt
5
0014H
Timer/Event Counter 1 Overflow
Interrupt
6
0018H
Suitable masking of the individual interrupts using the
interrupt registers can prevent simultaneous occur-
rences.
External Interrupt
For an external interrupt to occur, the global interrupt en-
able bit, EMI, and external interrupt enable bit, EEI,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, EIF is set,
a situation that will occur when a high to low transition
appears on the interrupt pins. The external interrupt pin
is pin-shared with the I/O pins PA6 can only be config-
ured as an external interrupt pin if the corresponding ex-
ternal interrupt enable bits in the interrupt control
register INTC0 have been set. The pins must also be
setup as inputs by setting the corresponding PAC.6 bits
in the port control register. When the interrupt is en-
abled, the stack is not full and a high to low transition ap-
pears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 08H will take
place. When the interrupt is serviced, the external inter-
rupt request flag, EIF will be automatically reset and the
EMI bit will be automatically cleared to disable other in-
terrupts. Note that any pull-high resistor configuration
options on these pins will remain valid even if the pins
are used as external interrupt inputs.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ETI0 or ETI1, must first be set. An
actual Timer/Event Counter interrupt will take place
when the Timer/Event Counter interrupt request flag,
TF0 or TF1, is set, a situation that will occur when the
Timer/Event Counter overflows. When the interrupt is
enabled, the stack is not full and a Timer/Event Counter
overflow occurs, a subroutine call to the timer interrupt
vector at location 0CH or 018H, will take place. When
the interrupt is serviced, the timer interrupt request flag,
TF0 or TF1, will be automatically reset and the EMI bit
will be automatically cleared to disable other interrupts.
SPI Interrupt
For an SPI Interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding SPI interrupt enable bit,
ESII_A or ESII_B, must be first set. An actual SPI Inter-
rupt will take place when one of the two SPI interrupt re-
quest flags, SIF_A or SIF_B, are set, a situation that will
occur when 8-bits of data are transferred or received
from either of the SPI interfaces. When the interrupt is
enabled, the stack is not full and an SPI_A interrupt oc-
curs, a subroutine call to the SPI_A interrupt vector at lo-
cation 10H, will take place. For an SPI_B interrupt, a
subroutine call to the SPI_B interrupt vector at location
14H, will take place. When the interrupt is serviced, the
SPI interrupt request flag, SIF_A or SIF_B, will be auto-
matically reset and the EMI bit will be automatically
cleared to disable other interrupts.
USB Interrupt
A USB interrupts will be triggered by the following USB
events, at which point the the related interrupt request
flag, USBF in the INTC0 register, will be set.
· Accessing the corresponding USB FIFO from the PC
· A USB suspend signal from the PC
· A USB resume signal from the PC
· A USB Reset signal
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag, USBF, and the
EMI bit will be cleared to disable other interrupts.
When PC Host accesses the FIFO of the device, the
corresponding request USR bit is set, and a USB inter-
rupt is triggered. Therefore it can be determined which
FIFO has been accessed. When the interrupt has been
served, the corresponding bit should be cleared by the
program. When the device receive a USB Suspend sig-
nal from the Host PC, the suspend line, bit0 of USC, is
set and a USB interrupt is also triggered. Also when de-
vice receive a Resume signal from the Host PC, the re-
sume line, bit3 of USC, is set and a USB interrupt is
triggered.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt control register until the corre-
sponding interrupt is serviced or until the request flag is
cleared by a software instruction.
Rev. 1.10
50
October 30, 2009