HT9170B_09 Datasheet, PDF (5/14 Pages) Holtek Semiconductor Inc – DTMF Receiver

T one 100kW
0 .1 m F
100kW
3 .5 7 9 5 4 5 M H z
20pF
20pF
V DD
0 .1 m F
1 _VP
V D D ¹⁸
2 _VN
R T /G T ^{1 7}
3 _GS
E S T ¹⁶
4 _VREF
D V ^{15 300kW}
5 _{IN H}
D 3 ¹⁴
6 _{PW DN}
D 2 ¹³
7 _X1
D 1 ¹²
8 _X2
D 0 ¹¹
9 _VSS
O E ¹⁰
H T 9 1 7 0 B /D
Figure 1. Test circuit
HT9170B/HT9170D
Functional Description
Overview
The HT9170B/D tone decoders consist of three band
pass filters and two digital decode circuits to convert a
tone (DTMF) signal into digital code output.
An operational amplifier is built-in to adjust the input sig-
nal (refer to Figure 2).
VP
C
R1
Vi
VN
RF
H T 9 1 7 0 B /D
GS
VREF
( a ) S ta n d a r d in p u t c ir c u it
C1 _R1
V i1
VP
V i2
VN
C2 R2
R3 R4 R5
H T 9 1 7 0 B /D
GS
VREF
( b ) D iffe r e n tia l in p u t c ir c u it
Figure 2. Input operation for amplifier application circuits
The pre-filter is a band rejection filter which reduces the
dialing tone from 350Hz to 400Hz.
The low group filter filters low group frequency signal
output whereas the high group filter filters high group
frequency signal output.
Each filter output is followed by a zero-crossing detector
with hysteresis. When each signal amplitude at the out-
put exceeds the specified level, it is transferred to full
swing logic signal.
When input signals are recognized to be effective, DV
becomes high, and the correct tone code (DTMF) digit is
transferred.
Steering control circuit
The steering control circuit is used for measuring the ef-
fective signal duration and for protecting against drop
out of valid signals. It employs the analog delay by exter-
nal RC time-constant controlled by EST.
The timing is shown in Figure 3. The EST pin is normally
low and draws the RT/GT pin to keep low through dis-
charge of external RC. When a valid tone input is de-
tected, EST goes high to charge RT/GT through RC.
When the voltage of RT/GT changes from 0 to V_TRT
(2.35V for 5V supply), the input signal is effective, and
the correct code will be created by the code detector. Af-
ter D0~D3 are completely latched, DV output becomes
high. When the voltage of RT/GT falls down from VDD to
V_TRT (i.e.., when there is no input tone), DV output be-
comes low, and D0~D3 keeps data until a next valid
tone input is produced.
By selecting adequate external RC value, the minimum ac-
ceptable input tone duration (t_ACC) and the minimum ac-
ceptable inter-tone rejection (t_IR) can be set. External
components (R, C) are chosen by the formula (refer to Fig-
ure 5.):
t_ACC=t_DP+t_GTP;
t_IR=t_DA+t_GTA;
where t_ACC: Tone duration acceptable time
t_DP: EST output delay time (²L²®²H²)
t_GTP: Tone present time
t_IR: Inter-digit pause rejection time
t_DA: EST output delay time (²H²®²L²)
t_GTA: Tone absent time
Rev. 1.11
5
February 23, 2009