HT9032C Datasheet, PDF (5/14 Pages) Holtek Semiconductor Inc – Calling Line Identification Receiver

HT9032C/HT9032D
Functional Description
The HT9032 is designed to be the physical layer de-
modulator for products targeted for the caller ID market.
The data signaling interface should conform to Bell 202,
which is described as follows:
· Analog, phase coherent, frequency shift keying
· Logical 1 (Mark)=1200+/-12Hz
· Logical 0 (Space)=2200+/-22Hz
· Transmission rate=1200bps
· Data application=serial, binary, asynchronous
The interface should be arranged to allow simple data
transmission from the terminating central office, to the
CPE (Customer Premises Equipment), only when the
CPE is in an on-hook state. The data will be transmitted
in the silent period between the first and second power
ring before a voice path is established. The transmission
level from the terminating C.O. will be -13.5dBm+/-1.0.
The worst case attenuation through the loop is expected
to be -20dB. The receiver therefore, should have a sen-
sitivity of approximately -34.5dBm to handle the worst
case installations. The ITU-T V.23 is also using the FSK
signaling scheme to transmit data in the general
switched telephone network. For mode 2 of the V.23, the
modulation rate and characteristic frequencies are listed
below:
· Analog, phase coherent, frequency shift keying
· Logical 1 (Mark)=1300Hz
· Logical 0 (Space)=2100Hz
· Transmission rate=1200bps
Since the band pass filter of the HT9032 can pass the
V.23 signal, hence the HT9032 also can demodulate the
V.23 signal.
Ring detection
The data will be transmitted in the silent period between
the first and second power ring before a voice path is es-
tablished. The HT9032 should first detect a valid ring
and then perform the FSK demodulation. The typical
ring detection circuit of the HT9032 is depicted below.
The power ring signal is first rectified through a bridge
circuit and then sent to a resistor network that attenu-
ates the incoming power ring. The values of resistors
and capacitor given in the figure have been chosen to
provide a sufficient voltage at RDET1 pin to turn on the
Schmitt trigger input with approximately a 40 Vrms or
greater power ring input from tip and ring. When V_T+ of
the Schmitt is exceeded, the NMOS on the pin RTIME
will be driven to saturation discharging capacitor on
RTIME. This will initialize a partial power up, with only
the portions of the part involved with the ring signal anal-
ysis enabled, including RDET2 pin. With RDET2 pin en-
abled, a portion of the power ring above 1.2V is fed to
the ring analysis circuit. Once the ring signal is qualified,
the RDET pin will be sent low.
PDW N
270kW
V DD
R T IM E
0 .2 m .
To
B r id g e
470kW
18kW
15kW
R D ET1
R D ET2
1 .2 V
P ow erU p
L o g ic
In te rn a l
P ow erU p
L o g ic
R in g
A n a ly s is
C ir c u it
RDET
Operation mode
There are three operation modes of the HT9032. They are power down mode, partial power up mode, and power up
mode. The three modes are classified by the following conditions:
Modes
Conditions
Current Consumption
Power down
PDWN=²1² and RTIME=²1²
<1mA
Partial power up
PDWN=²1² and RTIME=²0²
1.9mA typically
Power up
PDWN=²0²
3.2mA typically
Rev. 1.40
5
September 30, 2002