HT24LC08_14 Datasheet, PDF (5/12 Pages) Holtek Semiconductor Inc – CMOS 8K 2-Wire Serial EEPROM

HT24LC08
Write Operations
• Byte write
A write operation requires an 8-bit data word
address following the device address word and
acknowledgment. Upon receipt of this address,
the EEPROM will again respond with a zero
and then clock in the first 8-bit data word. After
receiving the 8-bit data word, the EEPROM will
output a zero and the addressing device, such as a
microcontroller, must terminate the write sequence
with a stop condition. At this time the EEPROM
enters an internally-timed write cycle to the non-
volatile memory. All inputs are disabled during this
write cycle and EEPROM will not respond until
the write is completed (refer to Byte write timing).
• Page write
The 8K EEPROM is capable of a 16-byte page
write. A page write is initiated in the same way as
a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked
in. Instead, after the EEPROM acknowledges the
receipt of the first data word, the microcontroller
can transmit up to 15 more data words. The
EEPROM will respond with a zero after each data
word received. The microcontroller must terminate
the page write sequence with a stop condition (refer
to Page write timing).
The data word address lower four bits are internally
incremented following the receipt of each data
word. The higher data word address bits are not
incremented, retaining the memory page row
location.
• Acknowledge polling
To maximise bus throughput, one technique is to
allow the master to poll for an acknowledge signal
after the start condition and the control byte for
a write command have been sent. If the device is
still busy implementing its write cycle, then no
ACK will be returned. The master can send the
next read/write command when the ACK signal
has finally been received.
• Write protect
The HT24LC08 has a write-protect function and
programming will then be inhibited when the WP
pin is connected to VCC. Under this mode, the
HT24LC08 is used as a serial ROM.
• Read operations
The HT24LC08 supports three read operations,
namely, current address read, random address
read and sequential read. During read operation
execution, the read/write select bit should be set to
"1".
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o n tro l B y te
w ith R /W = 0
(A C K = 0 )?
No
Y es
N e x t O p e r a tio n
Acknowledge Polling Flow
• Current address read
The internal data word address counter maintains
the last address accessed during the last read or
write operation, incremented by one. This address
stays valid between operations as long as the chip
power is maintained. The address roll over during
read from the last byte of the last memory page to
the first byte of the first page. The address roll over
during write from the last byte of the current page
to the first byte of the same page. Once the device
address with the read/write select bit set to one is
clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked
out. The microcontroller should respond with a "no
ACK" signal (high) followed by a stop condition
(refer to Current read timing).
• Random read
A random read requires a dummy byte write
sequence to load in the data word address which
is then clocked in and acknowledged by the
EEPROM. The microcontroller must then generate
another start condition. The microcontroller
now initiates a current address read by sending
a device address with the read/write select bit
high. The EEPROM acknowledges the device
address and serially clocks out the data word. The
microcontroller should respond with a "no ACK"
signal (high) followed by a stop condition. (refer
to Random read timing).
Rev. 1.80
5
January 16, 2014