HT1380 Datasheet, PDF (5/10 Pages) Holtek Semiconductor Inc – Serial Timekeeper Chip

HT1380/HT1381
The following table shows the register address and its data format:
Register Range
Register Definition
Address
Name Data _{D7 D6 D5 D4 D3 D2 D1 D0} A2~A0
Seconds 00~59 CH 10 SEC
SEC
000
Minutes 00~59 0
10 MIN
MIN
001
Hours
01~12 12\ 0 AP HR
00~23 24 0 10 HR
HOUR
010
Date
01~31 0 0 10 DATE
DATE
011
Month 01~12 0 0 0 10M
MONTH
100
Day
01~07 0 0 0 0
DAY
101
Year
00~99
10 YEAR
YEAR
110
Write
Protect
00~80 WP
ALWAYS ZERO
111
Bit
R/W
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
Command
Byte
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111
CH: Clock Halt bit
CH=0 oscillator enabled
CH=1 oscillator disabled
WP: Write protect bit
WP=0 register data can be written in
WP=1 register data can not be written in
Bit 7 of Reg2: 12/24 mode flag
bit 7=1, 12-hour mode
bit 7=0, 24-hour mode
Bit 5 of Reg2: AM/PM mode defined
AP=1 PM mode
AP=0 AM mode
R/W signal
The LSB of the Command Byte determines
whether the data in the register be read or be
written to.
When it is set as ²0² means that a write cycle is
to take place otherwise this chip will be set into
the read mode.
A0~A2
A0 to A2 of the Command Byte is used to specify
which registers are to be accessed. There are
eight registers used to control the month data,
etc., and each of these registers have to be set as
a write cycle in the initial time.
Burst mode
When the Command Byte is 10111110 (or
10111111), the HT1380/HT1381 is configured in
burst mode. In this mode the eight clock/calen-
dar registers can be written (or read) in series,
starting with bit 0 of register address 0 (see the
timing on the next page).
Test mode
When the Command Byte is set as 1001xxx1,
HT1380/HT1381 is configured in test mode.
The test mode is used by Holtek only for testing
purposes. If used generally, unpredictable con-
ditions may occur.
5
October 2, 1999