HT46R068B_15 Datasheet, PDF (49/135 Pages) Holtek Semiconductor Inc – Enhanced A/D 8-Bit OTP MCU

HT46R068B/HT46R069B
Enhanced A/D 8-Bit OTP MCU
• HT46R069B
Register
Name
PAWK
PAC
PAPU
PBC
PBPU
PCC
PCPU
PDC
PDPU
PEC
PEPU
PFC
PFPU
PGC
PGPU
PHC
PHPU
POR
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
3FH
00H
7
PAWK7
PAC7
—
PBC7
PBPU7
PCC7
PCPU7
PDC7
PDPU7
PEC7
PEPU7
PFC7
PFPU7
PGC7
PGPU7
—
—
6
PAWK6
PAC6
PAPU6
PBC6
PBPU6
PCC6
PCPU6
PDC6
PDPU6
PEC6
PEPU6
PFC6
PFPU6
PGC6
PGPU6
—
—
5
PAWK5
PAC5
PAPU5
PBC5
PBPU5
PCC5
PCPU5
PDC5
PDPU5
PEC5
PEPU5
PFC5
PFPU5
PGC5
PGPU5
PHC5
PHPU5
Bit
4
3
PAWK4 PAWK3
PAC4 PAC3
PAPU4 PAPU3
PBC4 PBC3
PBPU4 PBPU3
PCC4 PCC3
PCPU4 PCPU3
PDC4 PDC3
PDPU4 PDPU3
PEC4 PEC3
PEPU4 PEPU3
PFC4 PFC3
PFPU4 PFPU3
PGC4 PGC3
PGPU4 PGPU3
PHC4 PHC3
PHPU4 PHPU3
2
PAWK2
PAC2
PAPU2
PBC2
PBPU2
PCC2
PCPU2
PDC2
PDPU2
PEC2
PEPU2
PFC2
PFPU2
PGC2
PGPU2
PHC2
PHPU2
1
PAWK1
PAC1
PAPU1
PBC1
PBPU1
PCC1
PCPU1
PDC1
PDPU1
PEC1
PEPU1
PFC1
PFPU1
PGC1
PGPU1
PHC1
PHPU1
0
PAWK0
PAC0
PAPU0
PBC0
PBPU0
PCC0
PCPU0
PDC0
PDPU0
PEC0
PEPU0
PFC0
PFPU0
PGC0
PGPU0
PHC0
PHPU0
"—" Unimplemented, read as "0"
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn: Pull-high function enable
0: disable
1: enable
I/O Port Control Registers
Each Port has its own control register, known as PAC, PBC, PCC, PDC, PEC, PFC, PGC, PHC
which controls the input/output configuration. With this control register, each I/O pin with or without
pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to
function as an input, the corresponding bit of the control register must be written as a "1". This will
then allow the logic state of the input pin to be directly read by instructions. When the corresponding
bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin
is currently setup as an output, instructions can still be used to read the output register. However, it
should be noted that the program will in fact only read the status of the output data latch and not the
actual logic status of the output pin.
Rev. 1.50
49
February 05, 2015