HT86A36_12 Datasheet, PDF (48/68 Pages) Holtek Semiconductor Inc – A/D Type Voice 8-Bit MCU

HT86Axx/HT86ARxx
SPI Registers
There are two registers associated with the SPI Inter-
face. These are the SBCR register which is the control
register and the SBDR which is the data register. The
SBCR register is used to setup the required setup pa-
rameters for the SPI bus and also used to store associ-
ated operating flags, while the SBDR register is used for
data storage.
After Power on, the contents of the SBDR register will be
in an unknown condition while the SBCR register will de-
fault to the condition below:
CKS M1 M0 SBEN MLS CSEN WCOL TRF
0 11 0
0
0
0
0
Note that data written to the SBDR register will only be
written to the TXRX buffer, whereas data read from the
SBDR register will actual be read from the register.
SPI Bus Enable/Disable
To enable the SPI bus and CSEN=1, the SCK, SDI,
SDO and SCS lines should all be zero, then wait for data
to be written to the SBDR (TXRX bufffer) register. For
the Master Mode, after data has been written to the
SBDR (TXRX buffer) register then transmission or re-
ception will start automatically. When all the data has
been transferred the TRF bit should be set. For the
Slave Mode, when clock pulses are received on SCK,
data in the TXRX buffer will be shifted out or data on SDI
will be shifted in.
To Disable the SPI bus SCK, SDI, SDO, SCS floating.
SPI Operation
All communication is carried out using the 4-line inter-
face for both Master or Slave Mode. The timing diagram
shows the basic operation of the bus.
b7
CKS M 1
b0
M 0 S B E N M LS C S E N W C O L TR F
S B C R R e g is te r
T r a n s m itt/R e c e iv e F la g
0 : N o t c o m p le te
1 : T r a n s m is s io n /r e c e p tio n c o m p le te
W r ite C o llis io n B it
0 : C o llis io n fr e e
1 : C o llis io n d e te c te d
S e le c tio n S ig n a l E n a b le /D is a b le B it
0 : S C S flo a tin g
1 : E n a b le
M S B /L S B F ir s t B it
0 : L S B s h ift fir s t
1 : M S B s h ift fir s t
S e r ia l B u s E n a b le /D is a b le B it
0 : D is a b le
1 : E n a b le
D e p e n d e n t u p o n C S E N b it
M a s te r /S la v e /B a u d R a te B its
M1 M0
0
0 M a s te r , b a u d r a te : fS IO
0
1 M a s te r , b a u d r a te : fS IO /4
1
0 M a s te r , b a u d r a te : fS IO /1 6
1 1 S la v e m o d e
C lo c k S o u r c e S e le c t B it
0 : fS IO = fS Y S /4
1 : fS IO = fS Y S
SPI Interface Control Register
SCS
SCK
SDI
SDO
SCK
Rev. 1.10
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R ( if p u ll- h ig h e d )
S B E N = C S E N = 1 a n d w r ite d a ta to S B D R
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
SPI Bus Timing
48
December 12, 2012