BH66F5233 Datasheet, PDF (47/137 Pages) Holtek Semiconductor Inc – 24-Bit Delta Sigma A/D MCU

BH66F5233
24-Bit Delta Sigma A/D MCU
RSTFC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
RSTF LVRF
LRF
WRF
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
x
0
0
Bit 7~4 Unimplemented, read as "0"
"x": unknown
Bit 3
RSTF: Reset control register software reset flag
Describe elsewhere.
Bit 2
LVRF: LVR function reset flag
Described elsewhere.
Bit 1
LRF: LVR control register software reset flag
Described elsewhere.
Bit 0
WRF: WDT control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its timer overflows. This means
that in the application program and during normal operation the user has to strategically clear the
Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is
done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps
to an unknown location, or enters an endless loop, these clear instructions will not be executed in the
correct manner, in which case the Watchdog Timer will overflow and reset the device. There are five
bits, WE4~WE0, in the WDTC register to offer the enable/disable control and reset control of the
Watchdog Timer. The WDT function will be disabled when the WE4~WE0 bits are set to a value of
10101B while the WDT function will be enabled if the WE4~WE0 bits are equal to 01010B. If the
WE4~WE0 bits are set to any other values, other than 01010B and 10101B, it will reset the device
after a delay time, tSRESET. After power on these bits will have a value of 01010B.
WE4~WE0 Bits
10101B
01010B
Any other value
WDT Function
Disable
Enable
Reset MCU
Watchdog Timer Enable/Disable Control
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the
status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-
out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer
will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a
WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bits,
the second is using the Watchdog Timer software clear instruction, the third is via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single "CLR WDT" instruction to clear the WDT.
Rev. 1.00
47
June 30, 2016