HT45F12_12 Datasheet, PDF (45/103 Pages) Holtek Semiconductor Inc – 8-Bit Flash MCU with Op Amps & Comparators

HT45F12
8-Bit Flash MCU with Op Amps & Comparators
Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at
the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then
two possible situations may occur. The first is where the related interrupt is disabled or the interrupt
is enabled but the stack is full, in which case the program will resume execution at the instruction
following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not
be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled
or when a stack level becomes free. The other situation is where the related interrupt is enabled and
the stack is not full, in which case the regular interrupt response takes place. If an interrupt request
flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related
interrupt will be disabled.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to
unknown locations, due to certain uncontrollable external events such as electrical noise.
Watchdog Timer Clock Source
The Watchdog Timer clock source is provided by the internal clock, fS, which is in turn supplied by
the LIRC oscillator. The LIRC internal oscillator has an approximate period of 32 kHz at a supply
voltage of 5V. However, it should be noted that this specified internal clock period can vary with
VDD, temperature and process variations. The Watchdog Timer source clock is then subdivided by a
ratio of 2⁸ to 2¹⁸ to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in
the WDTC register.
Watchdog Timer Control Register
A single register, WDTC, controls the required timeout period as well as the enable/disable
operation. This register together with several configuration options control the overall operation of
the Watchdog Timer.
WDTC Register
Bit
7
Name
WE4
R/W
R/W
POR
0
6
WE3
R/W
1
5
WE2
R/W
0
4
WE1
R/W
1
3
WE0
R/W
0
2
WS2
R/W
0
1
WS1
R/W
1
0
WS0
R/W
1
Bit 7 ~ 3
WE4 ~ WE0: WDT enable bit
If the WDT configuration option is selected as “Always Enabled”:
10101 or 01010: Enabled
Other: Reset MCU
If the WDT configuration option is selected as “Application Program Enabled”:
10101: Disabled
01010: Enabled
Other Values: Reset MCU
If these bits are changed due to adverse environmental conditions, the microcontroller
will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the
WRF bit in the CTRL register will be set to 1.
Rev. 1.20
45
February 27, 2013