HT82A525R Datasheet, PDF (42/71 Pages) Holtek Semiconductor Inc – I/O Type USB 8-Bit OTP MCU with SPI

HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
MISC register combines a command and status to control the desired endpoint FIFO action and to
show the status of the desired endpoint FIFO. The MISC will be cleared by USB reset signal.
Bit No. Label
R/W
Function
FIFO request control bit
0
REQUEST
R/W
0: not requested; 1: requested
After selecting the desired endpoint, FIFO can be requested by setting this bit as high
active. Afterwards, this bit must be set low.
The direction and transition end indication bit
0: read data from FIFO; 1: write data to FIFO
This indicates the direction and transition end which the MCU accesses. When set
1
TX
R/W as logic ²1², the MCU writes data to FIFO. Afterwards, this bit must be set to logic ²0²
before terminating request to indicate transition end. For reading action, this bit must
be set to logic 0 to indicate that the MCU wants to read and must be set to logic ²1²
afterwards.
Clear requested FIFO control bit
0: not clear; 1: clear
2
CLEAR R/W This indicates an MCU clear requested FIFO, even if the FIFO is not ready. After
clearing the FIFO, USB interface will send force_tx_err to tell Host that data
under-run if Host wants to read data.
Serial DMA control bit
0: disable; 1: enable
3
SDMAEN
R/W
This bit is used to control the enable or disable the SBDR of the serial interfaces
(which is pin-shared with port E or port C) being written to FIFO3 directly.
SPI interfaces can be controlled by MCU and MCU can transmit or receive data by
writing or reading SBDR. It is allowed changing from 1 to 0 when the FIFO is not full.
Serial DMA interface selection bit
4 SDMASEL R/W 0: Serial interface 1 (pin-shared with port E)
1: Serial interface 2 (pin-shared with port C)
5
SETCMD
R/W
FIFO command data indication bit
0: not SETCMD token; 1: SETCMD token
6
READY
R
FIFO ready indication bit
0: not ready to work; 1: ready to work
7
LEN0
R/W
Host sent 0-sized packet indication bit
0: not 0-sized packet; 1: 0-sized packet
MISC (26H) Definitions
There are some timing constrains and usages illustrated here. By setting the MISC register, MCU
can perform reading, writing and clearing actions. There are some examples shown in the following
table for endpoint FIFO reading, writing and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay 2ms, check 41H®read* from FIFO0 register and
check not ready (01H)®03H®02H
Write FIFO0 sequence
02H®03H®delay 2ms, check 43H®write* to FIFO0 register and
check not ready (03H)®01H®00H
Check whether FIFO0 can be read or not 00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H
Check whether FIFO0 can be written or not 02H®03H®delay 2ms, check 43H (ready) or 03H (not ready)®02H
Write 0-sized packet sequence to FIFO0 02H®03H®delay 2ms, check 43H®01H®00H
Clear FIFO0 sequence
01H®delay 2ms®05H®delay 2ms®00H
Note: *: There are 2ms existing between 2 reading action or between 2 writing ® action.
Read or Write FIFO Table
Rev. 1.30
42
January 14, 2011