HT45R4U Datasheet, PDF (42/105 Pages) Holtek Semiconductor Inc – TinyPowerTM A/D Type e-Banking ASSP OTP MCU with LCD

HT45R4U
TinyPower^TM A/D Type
e-Banking ASSP OTP MCU with LCD
Bit 3
Bit 2~0
TnEG: Event Counter active edge select
0: count on rising edge
1: count on falling edge
Pulse Width Measurement active edge select
0: start counting on falling edge, stop on rising edge
1: start counting on rising edge, stop on falling edge
TnPSC[2:0]: Timer prescaler rate select
000: 1:1
001: 1:2
010: 1:4
011: 1:8
100: 1:16
101: 1:32
110: 1:64
111: 1:128
Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing
an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode,
the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the
correct value as shown. Control Register Operating Mode Select Bits for the Timer Mode
Bit7
Bit6
1
0
In this mode the internal clock, fSYS , is used as the internal clock for 8-bit Timer/Event Counters.
However, the clock source, fSYS, for the 8-bit timer is further divided by a prescaler, the value of
which is determined by the Prescaler Rate Select bits TnPSC2~TnPSC0, which are bits 2~0 in
the Timer Control Register. After the other bits in the Timer Control Register have been setup, the
enable bit TnON or TnON, which is bit 4 of the Timer Control Register, can be set high to enable
the Timer/Event Counter to run. Each time an internal clock cycle occurs, the Timer/Event Counter
increments by one. When it is full and overflows, an interrupt signal is generated and the Timer/
Event Counter will reload the value already loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the Timer/Event Counter Interrupt Enable bit in the
corresponding Interrupt Control Register, is reset to zero.
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
Timer Mode Timing Chart
T im e r + N
T im e r + N + 1
Rev. 1.10
42
March 12, 2015