HT45F3420 Datasheet, PDF (42/141 Pages) Holtek Semiconductor Inc – Personal Care Flash MCU

HT45F3420/HT45F3430
Personal Care Flash MCU
SMOD1 Register
Bit
7
6
5
4
3
Name FSYSON
─
─
─
─
R/W
R/W
─
─
─
─
POR
0
─
─
─
─
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Unimplemented, read as 0
LVRF: LVR function reset flag
Described elsewhere
Unimplemented, read as 0
WRF: WDT Control register software reset flag
Described elsewhere
2
LVRF
R/W
x
1
0
─
WRF
─
R/W
─
0
"x" unknown
Operating Mode Switching
The devices can switch between operating modes dynamically allowing the user to select the best
performance/power ratio for the present task in hand. In this way microcontroller operations that
do not require high performance can be executed using slower clocks thus requiring less operating
current and prolonging battery life in portable applications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the
HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/
SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT
instruction is executed, whether the devices enter the IDLE Mode or the SLEEP Mode is determined by
the condition of the IDLEN bit in the SMOD register and FSYSON in the SMOD1 register.
When the HLCLK bit switches to a low level, which implies that clock source is switched from the
high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high
speed clock source will stop running to conserve power. When this happens it must be noted that the
fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other
internal functions such as the TM.
NORMAL
f_SYS=f_H~f_H/64
f_H on
CPU run
f_SYS on
f_SUB on
IDLE1
HALT instruction executed
CPU stop
IDLEN=1
FSYSON=1
fSYS on
fSUB on
Rev. 1.31
SLEEP
HALT instruction executed
fSYS off
CPU stop
IDLEN=0
fTBC off
fSUB on
WDT on
SLOW
fSYS=fL
fL on
CPU run
fSYS on
fSUB on
fH off
42
IDLE0
HALT instruction executed
CPU stop
IDLEN=1
FSYSON=0
fSYS off
fSUB on
April 11, 2017