HT68F005 Datasheet, PDF (41/93 Pages) Holtek Semiconductor Inc – Enhanced I/O Flash Type MCU

HT68F005/HT68F006
Enhanced I/O Flash Type MCU
WDTC Register
Bit
Name
R/W
POR
Bit 7~3
Bit 2~0
7
WE4
R/W
0
6
WE3
R/W
1
5
WE2
R/W
0
4
WE1
R/W
1
3
WE0
R/W
0
2
WS2
R/W
0
1
WS1
R/W
1
0
WS0
R/W
1
WE4~WE0: WDT function software control
If the WDT configuration option is selected as “always enabled”:
10101 or 01010: WDT Enabled
Other values: Reset MCU
If the WDT configuration option is selected as “Controlled by the WDT control register”:
10101: WDT Disabled
01010: WDT Enabled
Other values: Reset MCU
When these bits are changed to any other values due to environmental noise the
microcontroller will be reset; this reset operation will be activated after 2~3 LIRC
clock cycles and the WRF bit in the CTRL register will be set to 1 to indicate the reset
source.
WS2, WS1, WS0: WDT time-out period selection
000: 256/fLIRC
001: 512/fLIRC
010: 1024/fLIRC
011: 2048/fLIRC
100: 4096/fLIRC
101: 8192/fLIRC
110: 16384/fLIRC
111: 32768/fLIRC
These three bits determine the division ratio of the Watchdog Timer source clock,
which in turn determines the timeout period.
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
FSYSON: fSYS Control in IDLE Mode
Described elsewhere
Unimplemented, read as “0”
LVRF: LVR function reset flag
Described elsewhere.
LRF: LVR Control register software reset flag
Described elsewhere.
WRF: WDT Control register software reset flag
0: Not occurred
1: Occurred
This bit is set to 1 by the WDT Control register software reset and cleared by the
application program. Note that this bit can only be cleared to 0 by the application
program.
Rev. 1.00
41
October 22, 2012