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HT48F06E Datasheet, PDF (31/69 Pages) Holtek Semiconductor Inc – I/O Flash Type MCU with EEPROM
HT48F06E/HT48F10E/HT48F30E
When the Timer/Event counter overflows, its corre-
sponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irre-
spective of whether the timer interrupt is enabled or not,
a Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condi-
tion. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these exter-
nal events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt re-
quest flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
Timer Program Example
This program example shows how the Timer/Event
Counter registers are setup, along with how the inter-
rupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter
tobe in the timer mode, which uses the internal system
clock as the clock source.
org 04h
; external interrupt vector
reti
org 08h
; Timer/Event Counter interrupt vector
jmp tmrint
; jump here when Timer overflows
:
org 20h
; main program
;internal Timer/Event Counter interrupt routine
tmrint:
:
; Timer/Event Counter main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,09bh
; setup preload value - timer counts from this value to FFH
mov tmr,a;
mov a,081h
; setup Timer control register
mov tmrc,a
; timer mode and prescaler set to /4
; setup interrupt register
mov a,005h
; enable master interrupt and timer interrupt
mov intc,a
set tmrc.4
; start Timer - note mode bits must be previously setup
Rev. 1.00
31
September 10, 2007