HT48RU80 Datasheet, PDF (30/54 Pages) Holtek Semiconductor Inc – I/O Type 8-Bit MCU

HT48RU80/HT48CU80
STOPS bits. If the break is much longer than 13 bit
times, the reception will be considered as complete
after the number of bit times specified by BNO and
STOPS. The RXIF bit is set, FERR is set, zeros are
loaded into the receive data register, interrupts are
generated if appropriate and the RIDLE bit is set. If
a long break signal has been detected and the re-
ceiver has received a start bit, the data bits and the
invalid stop bit, which sets the FERR flag, the re-
ceiver must wait for a valid stop bit before looking
for the next start bit. The receiver will not make the
assumption that the break condition on the line is
the next start bit. A break is regarded as a character
that contains only zeros with the FERR flag set. The
break character will be loaded into the buffer and no
further data will be received until stop bits are re-
ceived. It should be noted that the RIDLE read only
flag will go high when the stop bits have not yet
been received. The reception of a break character
on the UART registers will result in the following:
- _{The framing error flag, FERR, will be set.}
- _{The receive data register, RXR, will be cleared.}
- _{The OERR, NF, PERR, RIDLE or RXIF flags will}
possibly be set.
¨ Idle status
When the receiver is reading data, which means it
will be in between the detection of a start bit and the
reading of a stop bit, the receiver status flag in the
USR register, otherwise known as the RIDLE flag,
will have a zero value. In between the reception of a
stop bit and the detection of the next start bit, the
RIDLE flag will have a high value, which indicates
the receiver is in an idle condition.
¨ _{Receiver interrupt}
The read only receive interrupt flag RXIF in the USR
register is set by an edge generated by the receiver.
An interrupt is generated if RIE=1, when a word is
transferred from the Receive Shift Register, RSR, to
the Receive Data Register, RXR. An overrun error
can also generate an interrupt if RIE=1.
· _{Managing receiver errors}
Several types of reception errors can occur within the
UART module, the following section describes the
various types and how they are managed by the
UART.
¨ _{Overrun Error - OERR flag}
The RXR register is composed of a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO register, while a third byte can continue to be
received. Before this third byte has been entirely
shifted in, the data should be read from the RXR
register. If this is not done, the overrun error flag
OERR will be consequently indicated.
In the event of an overrun error occurring, the
following will happen:
- _{The OERR flag in the USR register will be set.}
- _{The RXR contents will not be lost.}
- _{The shift register will be overwritten.}
- _{An interrupt will be generated if the RIE bit is set.}
The OERR flag can be cleared by an access to the
USR register followed by a read to the RXR register.
¨ Noise Error - NF Flag
Over-sampling is used for data recovery to identify
valid incoming data and noise. If noise is detected
within a frame the following will occur:
- _{The read only noise flag, NF, in the USR register}
will be set on the rising edge of the RXIF bit.
- _{Data will be transferred from the Shift register to}
the RXR register.
- _{No interrupt will be generated. However this bit}
rises at the same time as the RXIF bit which itself
generates an interrupt.
Note that the NF flag is reset by a USR register read
operation followed by an RXR register read
operation.
¨ Framing Error - FERR Flag
The read only framing error flag, FERR, in the USR
register, is set if a zero is detected instead of stop
bits. If two stop bits are selected, both stop bits must
be high, otherwise the FERR flag will be set. The
FERR flag is buffered along with the received data
and is cleared on any reset.
¨ Parity Error - PERR Flag
The read only parity error flag, PERR, in the USR
register, is set if the parity of the received word is in-
correct. This error flag is only applicable if the parity
is enabled, PREN = 1, and if the parity type, odd or
even is selected. The read only PERR flag is buf-
fered along with the received data bytes. It is
cleared on any reset. It should be noted that the
FERR and PERR flags are buffered along with the
corresponding word and should be read before
reading the data word.
· _{UART interrupt scheme}
The UART internal function possesses its own inter-
nal interrupt and independent interrupt vector. Several
individual UART conditions can generate an internal
UART interrupt. These conditions are, a transmitter
data register empty, transmitter idle, receiver data
available, receiver overrun, address detect and an RX
pin wake-up. When any of these conditions are cre-
ated, if the UART interrupt is enabled and the stack is
not full, the program will jump to the UART interrupt
vector where it can be serviced before returning to the
main program. Four of these conditions, have a corre-
sponding USR register flag, which will generate a
UART interrupt if its associated interrupt enable flag in
the UCR2 register is set. The two transmitter interrupt
conditions have their own corresponding enable bits,
while the two receiver interrupt conditions have a
shared enable bit. These enable bits can be used to
mask out individual UART interrupt sources.
The address detect condition, which is also a UART
interrupt source, does not have an associated flag,
but will generate a UART interrupt when an address
detect condition occurs if its function is enabled by
setting the ADDEN bit in the UCR2 register. An RX pin
Rev. 1.00
30
April 12, 2006