HT66F0182 Datasheet, PDF (29/116 Pages) Holtek Semiconductor Inc – A/D 8-Bit Flash MCU

HT66F0182
A/D 8-Bit Flash MCU
Bit 1
Bit 0
IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
HLCLK: system clock selection
0: fH/2 ~ fH/64 or fSUB
1: fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as
the system clock. When the bit is high the fH clock will be selected and if low the
fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH
clock to the fSUB clock and the fH clock will be automatically switched off to conserve
power.
CTRL Register
Bit
7
6
5
4
3
Name FSYSON —
—
—
—
R/W
R/W
—
—
—
—
POR
0
—
—
—
—
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
Unimplemented, read as “0”
LVRF: LVR function reset flag
Described elsewhere
LRF: LVRC control register software reset flag
Described elsewhere
WRF: WDTC control register software reset flag
Described elsewhere
2
LVRF
R/W
x
1
0
LRF
WRF
R/W
R/W
0
0
“x”unknown
Rev. 1.00
29
December 17, 2015