HTG2190_02 Datasheet, PDF (27/50 Pages) Holtek Semiconductor Inc – 8-Bit 1024 Pixel Dot Matrix LCD MCU Series

HTG2190
BZ/SP
6/7
Bit
F1
0 0 F0
0 1 F0
1 0 F0
1 1 F0
F2
(Sampling
Rate)
F0/64
F0/128
F0/64
F0/128
Device
32W speaker
32W speaker
Buzzer/8W speaker
Buzzer/8W speaker
Note:
²F1² for PWM modulation clock and F2 for sam-
pling clock
²F0² f_SYS/(n+1) n=0~7 (n:3 bits preload counter)
On the above table, we can easily see that the sampling
rate is dependent on the system clock. If start bit is set to
²1², the PWM2 and PWM1 will output a GND level volt-
age.
Label
PWM dis/EN
BZ/SP
6/7 Bits
P0~P2
D0, D1
Bits
Function
0
Enable/disable PWM output
0: enable, 1: disable
1
Output driver select
1:buzzer ; 0:speaker
2
PWM counter bit select
1:7 bits ; 0:6 bits
3 bits preload counter
3~5 Bit543: 000B~111B (0~7)
Bit3: LSB
6, 7 PWMI
PWMC register
D1
D0
PWM Interrupt
0
0
1
0
1
2
1
0
4
1
1
8
The ratio of latch to interrupt
Bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
7-bit D7 D6 D5 D4 D3 D2 D1 D0
6-bit D7 D6 D5 D4 D3 D2 D1 X
PWM data buffer
Note: ²X² stands for don¢t care
bit7: Sign bit
Serial I/O interface function
The serial interface of the HTG2190 has two types of op-
eration mode: master mode and slave mode.
In the master mode, it uses an internal clock as synchro-
nous clock. In the slave mode, the synchronous output
from the external (master side) serial device is input.
The master mode and slave mode are selected through
registers SERC.2 and SERC.3; when the master mode
is selected, a synchronous clock may be selected from
among 2 types as shown in table.
SERC.3 SERC.2
Mode
Synchronous
Clock
1
1
Slave mode External clock
1
0
Master mode
SCLKS
0
1
Master mode
SCLKX
0
0
No used
.0
P W M d is /E N
L a tc h
.1
.2
32kH z
1 2 8 c lo c k
O n e s a m p lin g tim e
7 bits PWM counter bit
Rev. 1.20
27
July 5, 2002