HT49RA1_14 Datasheet, PDF (26/57 Pages) Holtek Semiconductor Inc – Remote Type 8-Bit MCU with LCD

HT49RA1/HT49CA1
to high transition. If T0E or T1E is high, the counter will
increment each time the external timer pin receives a
high to low transition. As in the case of the other two
modes, when the counter is full, the timer will overflow
and generate an internal interrupt signal. The counter
will then preload the value already loaded into the
preload register. As the external timer pins are
pin-shared with other I/O pins, to ensure that the pin is
configured to operate as an event counter input pin, two
things have to happen. The first is to ensure that the
T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event
Counter in the event counting mode, the second is to en-
sure that the port control register configures the pin as
an input. It should be noted that a timer overflow is one
of the interrupt and wake-up sources. Note that the timer
interrupts can be disabled by ensuring that the ET0I or
ET1I bits in the INTC0 or INTC1 register are reset to
zero.
b7
T0M 1 T0M 0 T0S T0O N T0E
b0
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
TM R 0C
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C o u n te r a c tiv e e d g e s e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
P u ls e W id th M e a s u r e m e n t a c tiv e e d g e s e le c t
1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e
0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1 : o p tio n c lo c k s o u r c e
0 : R T C in te r r u p t
O p e r a tin g m o d e s e le c t
T0M 1
0
0
1
1
T0M 0
0
1
0
1
n o m o d e a v a ila b le
e v e n t c o u n te r m o d e
tim e r m o d e
p u ls e w id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register - TMR0C
b7
T1M 1 T1M 0 T1S T1O N T1E
b0
T im e r /E v e n t C o u n te r C o n tr o l R e g is te r
TM R 1C
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C o u n te r a c tiv e e d g e s e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
P u ls e W id th M e a s u r e m e n t a c tiv e e d g e s e le c t
1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e
0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1:32768H z
0 : fS Y S /4
O p e r a tin g m o d e s e le c t
T1M 1 T1M 0
0
0 ^{n o m o d e a v a ila b le}
0
1 e v e n t c o u n te r m o d e
1
0 tim e r m o d e
1
1 p u ls e w id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register - TMR1C
Rev. 1.10
26
March 30, 2014