HT82R732 Datasheet, PDF (25/74 Pages) Holtek Semiconductor Inc – e-Banking 8-Bit OTP MCU

HT82R732
e-Banking 8-Bit OTP MCU
Wake-up
Source
External RES
PA, PB, PC Port
Interrupt
WDT Overflow
Oscillator Type
IRC
t_RSDT + t_SST1
t_SST1
Note:
1. t_RSTD (reset delay time), t_SYS (system clock)
2. t_RSTD is power-on delay, typical time=100ms
3. t_SST1= 16 or 1024 t_SYS, selected by the SSTC bit in the SYSC register.
Wake-up Delay Time
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by
the program jumping to unknown locations due to certain uncontrollable external events such as
electrical noise.
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when the Watchdog Timer counter
overflows.
The Watchdog Timer clock can emanate from three different sources, selected by the WCS1 and
WCS0 bits in the WDTC register. These are LXT, f_SYS/4 or LIRC. It is important to note that when the
system enters the HALT Mode the instruction clock is stopped, therefore if the WDTC register bits
have selected f_SYS/4 as the Watchdog Timer clock source, the Watchdog Timer will cease to function.
For systems that operate in noisy environments, using the LIRC or the LXT as the clock source is
therefore the recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2
of the WDTS register, known as WS0, WS1 and WS2. If the LIRC clock source is selected and with
the WS0, WS1 and WS2 bits of the WDTS register all set high, the prescaler division ratio will be
1:128, which will give a maximum time-out period.
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the
status bit TO. However, if the system is in the HALT Mode, when a Watchdog Timer time-out occurs,
the device will be woken up, the TO bit in the status register will be set and only the Program Counter
and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog
Timer. The first is an external hardware reset, which means a low level on the external reset pin. The
second is using the Clear Watchdog Timer software instructions and the third is when a HALT
instruction is executed. For a simple execution of ²CLR WDT² instruction will clear the Watchdog
Timer.
C LR W D T
fS Y S /4
LX T
L IR C
C LR
S /W
O p tio n
fS
8 s ta g e c o u n te r
C LR
7 - b it P r e s c a le r
W C S 1,W C S 0
8 -to -1 M U X
W S 0~W S 2
Watchdog Timer
W D T T im e - o u t
Rev. 1.00
25
October 31, 2013